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1.发明授权Clock tree in circuit having a power-mode control circuit to determine a first delay time and a second delay time 有权电路中的时钟树具有功率模式控制电路，以确定第一延迟时间和第二延迟时间公开(公告)号：US09477258B2
公开(公告)日：2016-10-25
申请号：US14509055
申请日：2014-10-08
申请人： Industrial Technology Research Institute , Chung Yuan Christian University , National Tsing Hua University
CPC分类号： G06F1/10
摘要： A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
摘要翻译： 提供电路中的时钟树及其操作方法。 时钟树包括至少两个子时钟树，至少两个电压可控功率模式感知（PMA）缓冲器和功率模式控制电路。 PMA缓冲器将系统时钟延迟用作延迟时钟，并分别向子时钟树提供延迟的时钟。 功率模式控制电路分别向至少两个功能模块提供至少两个第一功率信息，其中每个功能模块的功率模式分别根据第一功率信息来确定。 功率模式控制电路分别向PMA缓冲器提供至少两个第二功率信息，其中分别根据第二功率信息确定每个PMA缓冲器的延迟时间。
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公开(公告)号：US20150026490A1
公开(公告)日：2015-01-22
申请号：US14509055
申请日：2014-10-08
申请人： Industrial Technology Research Institute , Chung Yuan Christian University , National Tsing Hua University
CPC分类号： G06F1/10
摘要： A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
摘要翻译： 提供电路中的时钟树及其操作方法。 时钟树包括至少两个子时钟树，至少两个电压可控功率模式感知（PMA）缓冲器和功率模式控制电路。 PMA缓冲器将系统时钟延迟用作延迟时钟，并分别向子时钟树提供延迟的时钟。 功率模式控制电路分别向至少两个功能模块提供至少两个第一功率信息，其中每个功能模块的功率模式分别根据第一功率信息来确定。 功率模式控制电路分别向PMA缓冲器提供至少两个第二功率信息，其中分别根据第二功率信息确定每个PMA缓冲器的延迟时间。
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3.发明申请VOLTAGE-CONTROLLABLE POWER-MODE-AWARE CLOCK TREE, AND SYNTHESIS METHOD AND OPERATION METHOD THEREOF 审中-公开电压可控功率模式时钟树，及其合成方法及其操作方法公开(公告)号：US20140351616A1
公开(公告)日：2014-11-27
申请号：US14019546
申请日：2013-09-06
申请人： Industrial Technology Research Institute , National Tsing Hua University , Chung Yuan Christian University
IPC分类号： G06F1/32
CPC分类号： G06F1/10
摘要： A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.
摘要翻译： 提供集成电路（IC）中的电压可控功率模式感知（PMA）时钟树及其合成方法及其操作方法。 PMA时钟树包括至少两个子时钟树，至少两个PMA缓冲器和功率模式控制电路。 至少两个PMA缓冲器分别延迟系统时钟并将延迟的系统时钟提供给子时钟树作为延迟时钟。 功率模式控制电路分别向至少两个功能模块提供至少两个第一功率信息，以分别确定功能模块的功率模式。 功率模式控制电路分别向至少两个PMA缓冲器提供至少两个第二功率信息，以分别确定PMA缓冲器的延迟时间。
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公开(公告)号：US11294632B2
公开(公告)日：2022-04-05
申请号：US16861234
申请日：2020-04-29
发明人： Shih-Hsu Huang , Che-Wei Tung
摘要： A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N−1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N−1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.
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公开(公告)号：US20210096818A1
公开(公告)日：2021-04-01
申请号：US16861234
申请日：2020-04-29
发明人： Shih-Hsu Huang , Che-Wei Tung
摘要： A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N−1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N−1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.
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