公开(公告)号：US20240322812A1

公开(公告)日：2024-09-26

申请号：US18186515

申请日：2023-03-20

Applicant: Infineon Technologies AG

Inventor： Benjamin Schmidt

IPC: H03K17/082 ,  H03K17/06

CPC classification number: H03K17/0822 ,  H03K17/063 ,  H03K2217/0027

Abstract: Circuitry and techniques for detecting a circuit malfunction and disconnecting a main switch when the main switch comprises two or more smaller MOSFET switches connected in parallel. The circuitry of this disclosure includes a protection circuit switch using a protection switch arranged in parallel to the main switch. The protection switch circuit is configured to relieve the main switch MOSFETs as energy dissipates after the main switch circuit detects a fault and shuts off power to a load, but energy stored in the cable harness as inductance may cause current to continue to flow through the main switch MOSFETS. Dissipating this stored energy may result in an avalanche event in MOSFETs of the main switch. The protection circuit of this disclosure take more current shortly after the main switch turns OFF when the break-down voltages of the main switch MOSFETs may not be aligned.

公开(公告)号：US20240007084A1

公开(公告)日：2024-01-04

申请号：US17810163

申请日：2022-06-30

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Manuel Wilke ,  Benjamin Schmidt ,  Jonas Groenvall

IPC: H03K3/011 ,  H03K17/687

CPC classification number: H03K3/011 ,  H03K17/6871

Abstract: This disclosure is directed to a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material, and a second MOSFET formed in the semiconductor material, wherein the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, wherein the first MOSFET and the second MOSFET include a common drain node and a common source node, and wherein the first MOSFET and the second MOSFET define different transfer characteristics.

公开(公告)号：US11955974B2

公开(公告)日：2024-04-09

申请号：US17810163

申请日：2022-06-30

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Manuel Wilke ,  Benjamin Schmidt ,  Jonas Groenvall

IPC: H03K3/011 ,  H03K17/687

CPC classification number: H03K3/011 ,  H03K17/6871

Abstract: This disclosure is directed to a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material, and a second MOSFET formed in the semiconductor material, wherein the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, wherein the first MOSFET and the second MOSFET include a common drain node and a common source node, and wherein the first MOSFET and the second MOSFET define different transfer characteristics.