公开(公告)号：US10224919B2

公开(公告)日：2019-03-05

申请号：US15425599

申请日：2017-02-06

Applicant: Infineon Technologies AG

Inventor： Michael Asam ,  Carmelo Giunta

IPC: H03K17/06 ,  H03K17/284

Abstract: A power switch device includes a switch which is configured to switch a load signal between an on state and an off state. A first terminal and a second terminal of the power switch device are configured to provide a supply voltage to the power switch device. The second terminal is further configured to provide a control signal to the power switch device. The control signal is generated by disconnecting the second terminal from an external voltage source. A storage circuit of the power switch device is configured to capacitively store a status of the supply voltage. A control circuit of the power switch device is configured to control operation of the power switch device depending on the stored status of the supply voltage.

公开(公告)号：US20230261645A1

公开(公告)日：2023-08-17

申请号：US17651158

申请日：2022-02-15

Applicant: Infineon Technologies AG

Inventor： Marcus Nuebling ,  Carmelo Giunta

IPC: H03K17/04 ,  H03K17/0812

CPC classification number: H03K17/0406 ,  H03K17/08128

Abstract: A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

公开(公告)号：US20230017307A1

公开(公告)日：2023-01-19

申请号：US17377486

申请日：2021-07-16

Applicant: Infineon Technologies AG

Inventor： Carmelo Giunta ,  Marcus Nuebling ,  Steffen Thiele

IPC: G01R31/52 ,  H03K17/687 ,  G01R31/26

Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

公开(公告)号：US12009807B2

公开(公告)日：2024-06-11

申请号：US17651158

申请日：2022-02-15

Applicant: Infineon Technologies AG

Inventor： Marcus Nuebling ,  Carmelo Giunta

IPC: H03K17/04 ,  H03K17/0812

CPC classification number: H03K17/0406 ,  H03K17/08128 ,  H03F2203/45248

Abstract: A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

公开(公告)号：US11549998B1

公开(公告)日：2023-01-10

申请号：US17377486

申请日：2021-07-16

Applicant: Infineon Technologies AG

Inventor： Carmelo Giunta ,  Marcus Nuebling ,  Steffen Thiele

IPC: G01R31/52 ,  G01R31/26 ,  H03K17/687

Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

公开(公告)号：US20180226963A1

公开(公告)日：2018-08-09

申请号：US15425599

申请日：2017-02-06

Applicant: Infineon Technologies AG

Inventor： Michael Asam ,  Carmelo Giunta

IPC: H03K17/06 ,  H03K17/284

CPC classification number: H03K17/063 ,  H03K17/165 ,  H03K2217/0027

Abstract: A power switch device includes a switch which is configured to switch a load signal between an on state and an off state. A first terminal and a second terminal of the power switch device are configured to provide a supply voltage to the power switch device. The second terminal is further configured to provide a control signal to the power switch device. The control signal is generated by disconnecting the second terminal from an external voltage source. A storage circuit of the power switch device is configured to capacitively store a status of the supply voltage. A control circuit of the power switch device is configured to control operation of the power switch device depending on the stored status of the supply voltage.