公开(公告)号：US20200251400A1

公开(公告)日：2020-08-06

申请号：US15929296

申请日：2020-04-23

Applicant: Infineon Technologies AG

Inventor： Christian NEUGIRG ,  Peter SCHERL

IPC: H01L23/373 ,  H01L23/495 ,  H01L23/433 ,  H01L23/31 ,  H01L25/07 ,  H01L21/50 ,  H01L21/48

Abstract: A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

公开(公告)号：US20150264796A1

公开(公告)日：2015-09-17

申请号：US14214962

申请日：2014-03-16

Applicant: Infineon Technologies AG

Inventor： Christian NEUGIRG ,  Andreas GRASSMANN ,  Wolfram HABLE ,  Ottmar GEITNER ,  Frank WINTER ,  Alexander SCHWARZ ,  Inpil YOO

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/18

CPC classification number: H01L23/3733 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/373 ,  H01L23/49833 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/40137 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.

Abstract translation: 提供一种电子模块，其包括第一载体; 电子芯片，其包括至少一个电子部件并且布置在所述第一载体上; 间隔元件，包括布置在所述电子芯片上并与所述至少一个电子部件导热连接的表面; 布置在间隔元件上的第二载体; 以及至少部分地包围所述电子芯片和所述间隔元件的模具化合物; 其中所述间隔元件包括具有与至少一个其它CTE匹配的CTE值的材料。

公开(公告)号：US20210193556A1

公开(公告)日：2021-06-24

申请号：US17249325

申请日：2021-02-26

Applicant: Infineon Technologies AG

Inventor： Christian NEUGIRG ,  Peter SCHERL

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/50 ,  H01L25/07 ,  H01L23/495 ,  H01L23/31 ,  H01L23/433

Abstract: A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

公开(公告)号：US20190103342A1

公开(公告)日：2019-04-04

申请号：US15724920

申请日：2017-10-04

Applicant: Infineon Technologies AG

Inventor： Christian NEUGIRG ,  Peter Scherl

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.