公开(公告)号：US08956924B2

公开(公告)日：2015-02-17

申请号：US13925445

申请日：2013-06-24

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius C. Russ ,  Kai Esmark

IPC: H01L21/332 ,  H01L27/02 ,  H01L29/74 ,  H01L21/82

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract translation: 半导体器件包括设置在半导体本体内的SCR ESD器件区域，以及设置在第二导电类型的第二器件区域上的第一导电类型的多个第一器件区域，其中第二导电类型与第一导电类型相反 。 还包括具有第一导电类型的子区域和设置在第二器件区域上的第二导电类型的子区域的多个第三器件区域。 第一区域和第二区域分布成使得第三区域不直接相邻。 还包括与第二器件区域相邻的第一导电类型的第四器件区域和布置在第四器件区域内的第二导电类型的第五器件区域。

公开(公告)号：US20130277712A1

公开(公告)日：2013-10-24

申请号：US13925445

申请日：2013-06-24

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius C. Russ ,  Kai Esmark

IPC: H01L27/02 ,  H01L21/82

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.