公开(公告)号：US20160111413A1

公开(公告)日：2016-04-21

申请号：US14978882

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Jens Schneider ,  Kai Esmark ,  Martin Wendel

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/322

CPC classification number: H01L27/0255 ,  H01L21/26506 ,  H01L21/3221 ,  H01L23/62 ,  H01L27/0259 ,  H01L29/0603 ,  H01L29/32 ,  H01L29/66113 ,  H01L29/7302 ,  H01L29/861 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

Abstract translation: 本发明涉及可用作ESD保护装置的雪崩二极管。 在二极管的p-n结处形成雪崩点火区域，并且包括增强的缺陷浓度水平以提供雪崩电流的快速起始。 雪崩点火区优选地形成为比二极管耗尽区更宽，并且优选地通过优选通过离子注入放置与主要器件结构不同的原子物种来产生。 放置的原子物种的掺杂浓度应足够高，以确保超过二极管击穿电压时，雪崩电流基本上立即开始。 新的原子物质优选地包括氩或氮，但是可以使用其它原子物质。 然而，也考虑了增加二极管耗尽区中的缺陷浓度水平的其它方法，例如改变的退火程序。

公开(公告)号：US09257523B2

公开(公告)日：2016-02-09

申请号：US14304701

申请日：2014-06-13

Applicant: Infineon Technologies AG

Inventor： Jens Schneider ,  Kai Esmark ,  Martin Wendel

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/02 ,  H01L29/32 ,  H01L29/861 ,  H01L29/866 ,  H01L29/73 ,  H01L23/62

CPC classification number: H01L27/0255 ,  H01L21/26506 ,  H01L21/3221 ,  H01L23/62 ,  H01L27/0259 ,  H01L29/0603 ,  H01L29/32 ,  H01L29/66113 ,  H01L29/7302 ,  H01L29/861 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

Abstract translation: 本发明涉及可用作ESD保护装置的雪崩二极管。 在二极管的p-n结处形成雪崩点火区域，并且包括增强的缺陷浓度水平以提供雪崩电流的快速起始。 雪崩点火区优选地形成为比二极管耗尽区更宽，并且优选地通过优选通过离子注入放置与主要器件结构不同的原子物种来产生。 放置的原子物种的掺杂浓度应足够高，以确保超过二极管击穿电压时，雪崩电流基本上立即开始。 新的原子物质优选地包括氩或氮，但是可以使用其它原子物质。 然而，也考虑了增加二极管耗尽区中的缺陷浓度水平的其它方法，例如改变的退火程序。

公开(公告)号：US20180033783A1

公开(公告)日：2018-02-01

申请号：US15782582

申请日：2017-10-12

Applicant: Infineon Technologies AG

Inventor： Jens Schneider ,  Kai Esmark ,  Martin Wendel

IPC: H01L27/02 ,  H01L21/322 ,  H01L29/866 ,  H01L29/73 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/32 ,  H01L29/861 ,  H01L23/62

CPC classification number: H01L27/0255 ,  H01L21/26506 ,  H01L21/3221 ,  H01L23/62 ,  H01L27/0259 ,  H01L29/0603 ,  H01L29/32 ,  H01L29/66113 ,  H01L29/7302 ,  H01L29/861 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

公开(公告)号：US09263430B2

公开(公告)日：2016-02-16

申请号：US14606861

申请日：2015-01-27

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius Christian Russ ,  Kai Esmark

IPC: H01L27/00 ,  H01L27/02 ,  H01L29/74 ,  H01L21/82

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

公开(公告)号：US20150144996A1

公开(公告)日：2015-05-28

申请号：US14606861

申请日：2015-01-27

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius Christian Russ ,  Kai Esmark

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

公开(公告)号：US11121126B2

公开(公告)日：2021-09-14

申请号：US16775552

申请日：2020-01-29

Applicant: Infineon Technologies AG

Inventor： Christian Cornelius Russ ,  Markus Eckinger ,  Kai Esmark

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/74

Abstract: An embodiment of a silicon controlled rectifier (SCR) includes a semiconductor body, an active device region, and a device isolation region configured to electrically insulate the active device region from neighboring active device regions. First SCR regions and a second SCR region of a first conductivity type are in the active device region. A first pn-junction or Schottky junction is formed at an interface between the first SCR regions and the second SCR region. A first plurality of the first SCR regions and sub-regions of the second SCR region are alternately arranged and directly adjoin one another. A second pn-junction is formed at an interface between the second SCR region and a third SCR region of a second conductivity type. A third pn-junction is formed at an interface between the third SCR region and a fourth SCR region of the first conductivity type.

公开(公告)号：US08956924B2

公开(公告)日：2015-02-17

申请号：US13925445

申请日：2013-06-24

Applicant: Infineon Technologies AG

Inventor： Krzysztof Domanski ,  Cornelius C. Russ ,  Kai Esmark

IPC: H01L21/332 ,  H01L27/02 ,  H01L29/74 ,  H01L21/82

CPC classification number: H01L27/0262 ,  H01L21/82 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/74 ,  H01L29/7436 ,  H01L2924/13034

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract translation: 半导体器件包括设置在半导体本体内的SCR ESD器件区域，以及设置在第二导电类型的第二器件区域上的第一导电类型的多个第一器件区域，其中第二导电类型与第一导电类型相反 。 还包括具有第一导电类型的子区域和设置在第二器件区域上的第二导电类型的子区域的多个第三器件区域。 第一区域和第二区域分布成使得第三区域不直接相邻。 还包括与第二器件区域相邻的第一导电类型的第四器件区域和布置在第四器件区域内的第二导电类型的第五器件区域。

公开(公告)号：US09899367B2

公开(公告)日：2018-02-20

申请号：US15153276

申请日：2016-05-12

Applicant: Infineon Technologies AG

Inventor： Kai Esmark ,  Yiqun Cao ,  Donald Dibra

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7816

Abstract: An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.

公开(公告)号：US09812438B2

公开(公告)日：2017-11-07

申请号：US14978882

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Jens Schneider ,  Kai Esmark ,  Martin Wendel

IPC: H01L21/20 ,  H01L27/02 ,  H01L29/32 ,  H01L29/861 ,  H01L29/866 ,  H01L29/66 ,  H01L29/73 ,  H01L21/265 ,  H01L21/322 ,  H01L29/06 ,  H01L23/62

CPC classification number: H01L27/0255 ,  H01L21/26506 ,  H01L21/3221 ,  H01L23/62 ,  H01L27/0259 ,  H01L29/0603 ,  H01L29/32 ,  H01L29/66113 ,  H01L29/7302 ,  H01L29/861 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

公开(公告)号：US20160336308A1

公开(公告)日：2016-11-17

申请号：US15153276

申请日：2016-05-12

Applicant: Infineon Technologies AG

Inventor： Kai Esmark ,  Yiqun Cao ,  Donald Dibra

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/50 ,  H01L29/866 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/0255 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7816

Abstract: An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.

Abstract translation: 集成电路的实施例包括在半导体本体的第一表面处的半导体阱的最小横向尺寸。 集成电路还包括具有电耦合到负载引脚的负载路径的第一横向DMOSFET。 第一横向DMOSFET被配置为控制通过电耦合到负载引脚的负载元件的负载电流。 在半导体主体的第一表面处的第一横向DMOSFET的漏极区域的最小横向尺寸比最小横向尺寸大50％以上。