公开(公告)号：US12181361B2

公开(公告)日：2024-12-31

申请号：US17709934

申请日：2022-03-31

Applicant: Infineon Technologies AG

Inventor： Radu Mihaescu ,  Dan-Alexandru Mocanu ,  Ilie-Ionut Cristea

IPC: G01L27/00 ,  B60C23/04

Abstract: A pressure sensor module includes a pressure sensor configured to periodically measure an internal air pressure within an enclosure and generate a sensor signal having plurality of sensor values; a signal processing chain for conditioning the sensor signal to generate a plurality of conditioned sensor values; a memory configured to store each of the plurality of conditioned sensor values; and a processing circuit coupled to the pressure sensor via the signal processing chain for receiving a current conditioned sensor value and coupled to the memory for receiving a previous conditioned sensor value. The processing circuit is configured monitor for a fault, including calculating a delta pressure value between the current and previous conditioned sensor values, comparing the delta pressure value to a pressure threshold value, and triggering a diagnostic of the signal processing chain if the delta pressure value is greater than the pressure threshold value.

公开(公告)号：US12095119B2

公开(公告)日：2024-09-17

申请号：US17697143

申请日：2022-03-17

Applicant: Infineon Technologies AG

Inventor： Dan-Alexandru Mocanu ,  Bogdan Bumbacea ,  Ilie-Ionut Cristea ,  Radu Mihaescu

IPC: H01M50/578 ,  G01R31/396 ,  G06F13/42

CPC classification number: H01M50/578 ,  G01R31/396 ,  G06F13/4282

Abstract: A sensor device includes a pressure sensor configured to measure an internal air pressure and generate a sensor signal representative of the measured internal air pressure; a serial peripheral interface (SPI) configured to receive SPI commands; a wake-up terminal configured to output fault signals; and a processing circuit. The processing circuit is configurable between a normal running mode and a low power monitoring (LPM) mode. In LPM mode, the processing circuit is configured to alternate between a sampling phase during which the processing circuit evaluates the sensor signal and a powered-down phase during which the processing circuit is in a low power state. The processing circuit is configured to monitor for at least one SPI communication fault corresponding to information received on the SPI, generate a communication fault signal in response to detecting the at least one SPI communication fault, and output the communication fault signal from the wake-up terminal.

公开(公告)号：US11165414B2

公开(公告)日：2021-11-02

申请号：US16723223

申请日：2019-12-20

Applicant: Infineon Technologies AG

Inventor： Victor Popescu-Stroe ,  Dan-Alexandru Mocanu

IPC: H03H17/02

Abstract: A filter circuit includes a first stage comprising a first infinite impulse response (IIR) filter; a third stage comprising a third IIR filter; and a second stage interposed between the first stage and the third stage, the second stage comprising a second IIR filter, where an output terminal of the first IIR filter is coupled to an input terminal of the second IIR filter, and an output terminal of the second IIR filter is coupled to an input terminal of the third IIR filter, where the second stage of the filter circuit is configured to operate in an acquisition mode when a transient is detected in an input signal to the first IIR filter, where during the acquisition mode, the second stage of the filter circuit is bypassed.

公开(公告)号：US20210194465A1

公开(公告)日：2021-06-24

申请号：US16723223

申请日：2019-12-20

Applicant: Infineon Technologies AG

Inventor： Victor Popescu-Stroe ,  Dan-Alexandru Mocanu

IPC: H03H17/02

Abstract: A filter circuit includes a first stage comprising a first infinite impulse response (IIR) filter; a third stage comprising a third IIR filter; and a second stage interposed between the first stage and the third stage, the second stage comprising a second IIR filter, where an output terminal of the first IIR filter is coupled to an input terminal of the second IIR filter, and an output terminal of the second IIR filter is coupled to an input terminal of the third IIR filter, where the second stage of the filter circuit is configured to operate in an acquisition mode when a transient is detected in an input signal to the first IIR filter, where during the acquisition mode, the second stage of the filter circuit is bypassed.