公开(公告)号：US20240176589A1

公开(公告)日：2024-05-30

申请号：US18519795

申请日：2023-11-27

Applicant: Infineon Technologies AG

Inventor： Florian Mendel ,  Franz Klug

IPC: G06F7/544

CPC classification number: G06F7/5443

Abstract: A processing circuit comprises a first multiplier configured to determine three shares of the product of the first operand with a blinding value by multiplying each share of the first operand with each share of the blinding value according to a first split of the blinding value into three first shares. The processing circuit further comprises one or more first adders configured to determine, for each share of the second operand, the sum of the share of the second operand with a respective corresponding second share of the blinding value according to a second split of the blinding value into three second shares, wherein the first and second splits of the blinding value are different. The processing circuit is configured to determine shares of the product of the first operand with the second operand from the results of the first multiplier and the one or more first adders.

公开(公告)号：US20190243789A1

公开(公告)日：2019-08-08

申请号：US16258710

申请日：2019-01-28

Applicant: Infineon Technologies AG

Inventor： Gerd Dirscherl ,  Benedikt Driessen ,  Gunther Fenzl ,  Franz Klug ,  Bernd Meyer ,  Steffen Sonnekalb

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F2213/40

Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

公开(公告)号：US11171647B2

公开(公告)日：2021-11-09

申请号：US15931966

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel ,  Franz Klug

IPC: H03K19/003 ,  H03K19/094

Abstract: According to one embodiment, an integrated electronic circuit has a switching network configured to receive binary control states, one or more secret-carrying gates, wherein each secret-carrying gate represents Boolean secrets and is configured to receive binary input states and to output one or more Boolean secrets according to a state sequence of the binary input states, and one or more flip-flops configured to store binary output states output by the switching network and to supply binary input states to the one or more secret-carrying gates based on the stored binary output states. The switching network generates the binary output states by combining the binary control states and Boolean secrets output by the one or more secret-carrying gates. The integrated electronic circuit outputs Boolean secrets from the one or more secret-carrying gates and/or the binary output states from the switching network to another integrated electronic circuit.

公开(公告)号：US10649931B2

公开(公告)日：2020-05-12

申请号：US16258710

申请日：2019-01-28

Applicant: Infineon Technologies AG

Inventor： Gerd Dirscherl ,  Benedikt Driessen ,  Gunther Fenzl ,  Franz Klug ,  Bernd Meyer ,  Steffen Sonnekalb

IPC: G06F13/20 ,  G06F21/60

Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

公开(公告)号：US09806881B2

公开(公告)日：2017-10-31

申请号：US14316833

申请日：2014-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel ,  Franz Klug

IPC: G06F21/00 ,  H04L9/06 ,  H04L9/00 ,  G06F21/72

CPC classification number: H04L9/0618 ,  G06F21/72 ,  H04L9/003 ,  H04L9/0643 ,  H04L2209/046

Abstract: A cryptographic processor is described comprising a processing circuit configured to perform a round function of an iterated cryptographic algorithm, a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm and a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration wherein the transformation circuit is implemented using a circuit camouflage technique.

公开(公告)号：US10395063B2

公开(公告)日：2019-08-27

申请号：US15272458

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Franz Klug ,  Thomas Kuenemund

IPC: H04L29/06 ,  G06F21/71 ,  G06F7/00 ,  G06F21/55 ,  G06F21/62 ,  H04L9/00 ,  H03K5/1536 ,  H03K5/22

Abstract: A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.

公开(公告)号：US20150381351A1

公开(公告)日：2015-12-31

申请号：US14316833

申请日：2014-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel ,  Franz Klug

IPC: H04L9/06 ,  H04L9/32 ,  G06F21/60

CPC classification number: H04L9/0618 ,  G06F21/72 ,  H04L9/003 ,  H04L9/0643 ,  H04L2209/046

Abstract: A cryptographic processor is described comprising a processing circuit configured to perform a round function of an iterated cryptographic algorithm, a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm and a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration wherein the transformation circuit is implemented using a circuit camouflage technique.

Abstract translation: 描述了一种加密处理器，其包括被配置为执行迭代密码算法的循环函数的处理电路，被配置为控制处理电路以对循环函数应用多个迭代以对消息进行处理的处理电路，该处理电路根据 迭代密码算法和变换电路，被配置为在所述多个迭代的循环函数的第一迭代之后变换所述循环函数的第二迭代的输入，并将所述变换输入作为输入提供给所述第二迭代，其中所述变换电路为 使用电路伪装技术实现。

公开(公告)号：US09165162B2

公开(公告)日：2015-10-20

申请号：US13729052

申请日：2012-12-28

Applicant: Infineon Technologies AG

Inventor： Franz Klug ,  Steffen Sonnekalb

IPC: H04L29/06 ,  G06F21/73 ,  G06F13/38 ,  G06F21/57 ,  G06F21/64

CPC classification number: G06F21/73 ,  G06F13/38 ,  G06F21/57 ,  G06F21/64 ,  G06F21/85

Abstract: A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.

Abstract translation: 提供了一种处理器装置。 处理器布置包括：第一处理器; 多个第二处理器，每个第二处理器包括被配置为产生处理器专用位掩码序列的位掩码生成器; 其中所述第一处理器包括被配置为生成所述第二处理器的处理器特定位掩码序列的位掩码生成器; 其中所述第一处理器被配置为使用特定于所述一个第二处理器的特定于处理器的位掩码序列对要发送到所述多个第二处理器的一个第二处理器的数据位序列进行位掩码，从而生成处理器特定的 位传送到一秒处理器的位掩码数据序列。

公开(公告)号：US20140189176A1

公开(公告)日：2014-07-03

申请号：US13729052

申请日：2012-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Franz Klug ,  Steffen Sonnekalb

IPC: G06F13/38

CPC classification number: G06F21/73 ,  G06F13/38 ,  G06F21/57 ,  G06F21/64 ,  G06F21/85

Abstract: A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.

Abstract translation: 提供了一种处理器装置。 处理器布置包括：第一处理器; 多个第二处理器，每个第二处理器包括被配置为产生处理器专用位掩码序列的位掩码生成器; 其中所述第一处理器包括被配置为生成所述第二处理器的处理器特定位掩码序列的位掩码生成器; 其中所述第一处理器被配置为使用特定于所述一个第二处理器的特定于处理器的位掩码序列对要发送到所述多个第二处理器的一个第二处理器的数据位序列进行位掩码，从而生成处理器特定的 位传送到一秒处理器的位掩码数据序列。