公开(公告)号：US11217658B2

公开(公告)日：2022-01-04

申请号：US16423535

申请日：2019-05-28

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Grzegorz Kozlowski ,  Till Schloesser

IPC: H01L49/02 ,  H01L21/761 ,  H01L21/762

Abstract: The disclosure relates to a semiconductor device, including a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, the second conductivity type being different than the first conductivity type. The semiconductor device also includes an isolation structure electrically isolating a first region of the semiconductor layer from a second region of the semiconductor layer. A shallow trench isolation structure vertically extends from a surface of the semiconductor layer into the first region of the semiconductor layer. An electrical resistor is formed on the shallow trench isolation structure.

公开(公告)号：US20190189743A1

公开(公告)日：2019-06-20

申请号：US16220592

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Grzegorz Kozlowski

IPC: H01L29/08 ,  H01L29/735 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/735 ,  H01L29/7835

Abstract: The disclosure relates to a planar field effect transistor. The planar field effect transistor includes a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. The planar field effect transistor also includes a first electrode part and a second electrode part laterally spaced apart from the first electrode part. The first electrode part is arranged as a gate electrode above the channel region. The second electrode part is arranged above the drain extension region and is electrically isolated from the first electrode part.