公开(公告)号：US20040185631A1

公开(公告)日：2004-09-23

申请号：US10757360

申请日：2004-01-13

Applicant: Infineon Technologies AG

Inventor： Jakob Kriz ,  Martin Seck ,  Armin Tilke

IPC: H01L021/331 ,  H01L021/8222

CPC classification number: H01L29/66272 ,  H01L21/2257

Abstract: In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an insulating material will now be applied, wherein the at least one layer is patterned such that at least one section of the basis region is exposed. Next, a layer of a polycrystalline semiconductor material of the first conductivity type, which is heavily doped with doping atoms, will be generated such that the exposed section is essentially covered. Now, a second layer of a highly conductive material on the layer of the polycrystalline semiconductor material will be generated in order to form an emitter double layer with the same. Thereupon, at least part of the doping atoms of the first conductivity type of the heavily doped polycrystalline semiconductor layer is caused to get into the basis region to generate an emitter region of the first conductivity type.

Abstract translation: 在本发明的制造具有多晶硅发射极的双极晶体管的方法中，首先将产生第一导电类型的集电极区域，并与其邻接的第二导电类型的基极区域。 现在将施加至少一层绝缘材料，其中图案化至少一个层使得基础区域的至少一个部分被暴露。 接下来，将产生重掺杂掺杂原子的第一导电类型的多晶半导体材料层，使得暴露部分基本上被覆盖。 现在，将产生多晶半导体材料层上的高导电材料的第二层，以便形成具有该多层半导体材料的发射极双层。 因此，引起重掺杂多晶半导体层的第一导电类型的掺杂原子的至少一部分进入基区以产生第一导电类型的发射极区。

公开(公告)号：US20030015752A1

公开(公告)日：2003-01-23

申请号：US09927573

申请日：2001-08-09

Applicant: Infineon Technologies AG

Inventor： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

IPC: H01L021/8238 ,  H01L029/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

Abstract translation: 每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。 栅电极通过介电材料与半导体材料分离。 至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氮化物 - 氧化物层序列。 层序列是为了在源极和漏极处俘获电荷载体而提供的。