公开(公告)号：US20030015752A1

公开(公告)日：2003-01-23

申请号：US09927573

申请日：2001-08-09

Applicant: Infineon Technologies AG

Inventor： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

IPC: H01L021/8238 ,  H01L029/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

Abstract translation: 每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。 栅电极通过介电材料与半导体材料分离。 至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氮化物 - 氧化物层序列。 层序列是为了在源极和漏极处俘获电荷载体而提供的。

公开(公告)号：US20030151091A1

公开(公告)日：2003-08-14

申请号：US10378101

申请日：2003-02-28

Applicant: Infineon Technologies AG

Inventor： Herbert Palm ,  Josef Willer

IPC: H01L029/76

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L29/66833

Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W. .

Abstract translation: 导电层或层序列优选地包括施加到金属硅化物或多晶硅层的含金属层以降低掩埋位线的电阻。 层或层序列已经以带状形式图案化，以对应于位线，并且布置在具有ONO存储层序列的存储晶体管的源极/漏极区域和布置在沟槽中的栅极电极。 金属硅化物优选为硅化钴，并且含金属层优选为硅化钨或WN / W。 。