公开(公告)号：US20190074243A1

公开(公告)日：2019-03-07

申请号：US15694086

申请日：2017-09-01

Applicant: Infineon Technologies AG

Inventor： Rainald SANDER ,  Liu CHEN ,  Teck Sim LEE

IPC: H01L23/495 ,  H01L23/00

Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.

公开(公告)号：US20210398867A1

公开(公告)日：2021-12-23

申请号：US16906617

申请日：2020-06-19

Applicant: Infineon Technologies AG

Inventor： Edward MYERS ,  Liu CHEN ,  Chee Chiew CHONG ,  Wee Aun Jason LIM ,  Wee Boon TAY

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.