公开(公告)号：US20210398867A1

公开(公告)日：2021-12-23

申请号：US16906617

申请日：2020-06-19

Applicant: Infineon Technologies AG

Inventor： Edward MYERS ,  Liu CHEN ,  Chee Chiew CHONG ,  Wee Aun Jason LIM ,  Wee Boon TAY

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

公开(公告)号：US20170317036A1

公开(公告)日：2017-11-02

申请号：US15582646

申请日：2017-04-29

Applicant: Infineon Technologies AG

Inventor： Edward MYERS ,  Thomas BEMMERL ,  Melissa STAHL

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.