公开(公告)号：US11158707B2

公开(公告)日：2021-10-26

申请号：US17010668

申请日：2020-09-02

Applicant: Infineon Technologies AG

Inventor： Hanno Melzner ,  Markus Dankerl ,  Peter Irsigler ,  Sebastian Schmidt ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/43

Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.

公开(公告)号：US20210118992A1

公开(公告)日：2021-04-22

申请号：US17010668

申请日：2020-09-02

Applicant: Infineon Technologies AG

Inventor： Hanno Melzner ,  Markus Dankerl ,  Peter Irsigler ,  Sebastian Schmidt ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/43 ,  H01L29/423

Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.