公开(公告)号：US20240312956A1

公开(公告)日：2024-09-19

申请号：US18122776

申请日：2023-03-17

Applicant: Infineon Technologies AG

Inventor： Pei Luan Pok ,  Swee Kah Lee ,  Soon Lock Goh ,  Chee Hong Lee ,  Samsun Paing ,  Chee Chiew Chong

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L2224/11 ,  H01L2224/96

Abstract: A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.