公开(公告)号：US20200327007A1

公开(公告)日：2020-10-15

申请号：US16849493

申请日：2020-04-15

Applicant: Infineon Technologies AG

Inventor： Rex Kho ,  Udo Elsholz

IPC: G06F11/07 ,  H03K5/24 ,  H03K21/08 ,  G06F1/06

Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

公开(公告)号：US11487600B2

公开(公告)日：2022-11-01

申请号：US16849493

申请日：2020-04-15

Applicant: Infineon Technologies AG

Inventor： Rex Kho ,  Udo Elsholz

IPC: G06F11/00 ,  G06F11/07 ,  H03K5/24 ,  G06F1/06 ,  H03K21/08

Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

公开(公告)号：US10735006B1

公开(公告)日：2020-08-04

申请号：US16451317

申请日：2019-06-25

Applicant: Infineon Technologies AG

Inventor： Rex Kho ,  Udo Elsholz

IPC: H03L7/099 ,  G06F1/08

Abstract: A functional clock generator, including: an oscillator configured to generate an oscillator clock having an oscillator clock frequency; a control value generator configured to generate control values to ramp the oscillator clock frequency between a first frequency and a second, higher frequency; a Phase-Locked Loop (PLL) configured to generate a PLL clock having the second frequency; and a selector configured to switch between selecting the oscillator clock and the PLL clock as a functional clock when the oscillator clock frequency and the PLL clock frequency are substantially equal.