中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.014 seconds)

    Burn-in testing of circuits
    1.
    发明授权
    Burn-in testing of circuits 有权

    公开(公告)号：US10180455B2

    公开(公告)日：2019-01-15

    申请号：US15601716

    申请日：2017-05-22

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Markus Schuemmer ,  Human Boluki

    IPC: G01R31/28

    Abstract: Circuits and methods are provided for a signal path between circuit parts. During normal operation, a delay is deactivated. During a burn-in test, the delay is activated. In the deactivated state, a delay component may be disconnected from a supply voltage.

    Electronic circuit
    2.
    发明授权
    Electronic circuit 有权

    公开(公告)号：US11487600B2

    公开(公告)日：2022-11-01

    申请号：US16849493

    申请日：2020-04-15

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Udo Elsholz

    IPC: G06F11/00 ,  G06F11/07 ,  H03K5/24 ,  G06F1/06 ,  H03K21/08

    Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

    Method and device for processing an erase counter
    3.
    发明授权
    Method and device for processing an erase counter 有权
    用于处理擦除计数器的方法和设备

    公开(公告)号：US09466377B2

    公开(公告)日：2016-10-11

    申请号：US14190265

    申请日：2014-02-26

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Mathew Neal

    IPC: G11C16/10 ,  G11C14/00 ,  G11C7/24 ,  G06F21/55 ,  G11C16/34 ,  G11C16/14

    CPC classification number: G11C16/107 ,  G06F21/554 ,  G11C7/24 ,  G11C14/009 ,  G11C16/14 ,  G11C16/3495

    Abstract: A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory.

    Abstract translation: 一个实施例涉及一种用于处理包括擦除计数器字段的擦除计数器的方法，该方法包括以下步骤：（i）确定未使用的擦除计数器字段; （ii）在未使用的擦除计数器字段中写入选择代码和地址信息，其中组合选择代码和地址信息以确定存储器的至少一个物理地址。

    TIME MEASUREMENT OF A CLOCK-BASED SIGNAL
    5.
    发明申请
    TIME MEASUREMENT OF A CLOCK-BASED SIGNAL 有权

    公开(公告)号：US20220085824A1

    公开(公告)日：2022-03-17

    申请号：US17467767

    申请日：2021-09-07

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Ketan Dewan ,  Rex Kho ,  Ralph Mueller-Eschenbach ,  Juergen Schaefer

    IPC: H03M1/12 ,  G06F1/10 ,  G01R31/317

    Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

    ELECTRONIC CIRCUIT
    6.
    发明申请
    ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：US20200327007A1

    公开(公告)日：2020-10-15

    申请号：US16849493

    申请日：2020-04-15

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Udo Elsholz

    IPC: G06F11/07 ,  H03K5/24 ,  H03K21/08 ,  G06F1/06

    Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

    System and method for integrated circuit clock distribution
    7.
    发明授权
    System and method for integrated circuit clock distribution 有权
    集成电路时钟分配的系统和方法

    公开(公告)号：US09490787B1

    公开(公告)日：2016-11-08

    申请号：US14737224

    申请日：2015-06-11

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Andreas Weisgerber ,  Dirk Hesidenz

    IPC: H04L7/00 ,  H03K5/135 ,  H03L7/081 ,  H03L7/091 ,  H03K5/00

    CPC classification number: H03K5/135 ,  H03K2005/00019

    Abstract: An embodiment integrated circuit (IC) clock distributor system includes a first IC. The first IC includes a clock synchronizer circuit and a clock generator circuit. The clock synchronizer circuit includes a first input coupled to a first clock transfer path including a replica delay of a portion of a first signal path included in an external IC. The clock synchronizer circuit also includes a second input coupled to a second clock transfer path. The clock generator circuit also includes an input coupled to an output of at least one of a reference oscillator and the clock synchronizer circuit. Delay of the second clock transfer path includes delay of the first signal path.

    Abstract translation: 实施例集成电路（IC）时钟分配器系统包括第一IC。 第一IC包括时钟同步器电路和时钟发生器电路。 时钟同步器电路包括耦合到包括外部IC中包括的第一信号路径的一部分的复制延迟的第一时钟传送路径的第一输入。 时钟同步器电路还包括耦合到第二时钟传送路径的第二输入。 时钟发生器电路还包括耦合到参考振荡器和时钟同步器电路中的至少一个的输出的输入。 第二时钟传送路径的延迟包括第一信号路径的延迟。

    Method of Detecting Bit Errors, An Electronic Circuit for Detecting Bit Errors, and a Data Storage Device
    8.
    发明申请
    Method of Detecting Bit Errors, An Electronic Circuit for Detecting Bit Errors, and a Data Storage Device 有权
    检测位错误的方法，用于检测位错误的电子电路和数据存储设备

    公开(公告)号：US20150100827A1

    公开(公告)日：2015-04-09

    申请号：US14045923

    申请日：2013-10-04

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Thomas Rabenalt

    IPC: G06F11/07

    CPC classification number: G06F11/1024 ,  G06F11/08 ,  H03M13/03

    Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.

    Abstract translation: 提供了一种检测数据存储装置中的比特错误的方法，其包括将在数据存储装置的读出操作期间访问的第一比特序列与对应于数据存储装置的预期存储状态的第二比特序列进行比较。

Patent Agency Ranking