公开(公告)号：US20230361088A1

公开(公告)日：2023-11-09

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L25/072 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

公开(公告)号：US20200321262A1

公开(公告)日：2020-10-08

申请号：US16839683

申请日：2020-04-03

Applicant: Infineon Technologies AG

Inventor： Christian Schweikert ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Waldemar Jakobi

IPC: H01L23/367 ,  G01K1/14 ,  H01L21/48

Abstract: A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.

公开(公告)号：US10692806B2

公开(公告)日：2020-06-23

申请号：US16179015

申请日：2018-11-02

Applicant: Infineon Technologies AG

Inventor： Waldemar Jakobi ,  Christoph Koch

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L23/538 ,  H01L25/18 ,  H01L23/373

Abstract: A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base section and first, second and third sections, the third section arranged between the first and second sections. The second conductor track has first and second sections. The first section of the second conductor track is arranged between the first and third sections of the first conductor track. The second section of the second conductor track is arranged between the second and third sections of the first conductor track. The third section of the first conductor track is arranged between the first and second sections of the second conductor track. First and second subsets of semiconductor chips are arranged on the first section of the second conductor track. Third and fourth subsets of semiconductor chips are arranged on the second section of the second conductor track.

公开(公告)号：US20250062290A1

公开(公告)日：2025-02-20

申请号：US18934846

申请日：2024-11-01

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bãßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498

Abstract: A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.

公开(公告)号：US11610830B2

公开(公告)日：2023-03-21

申请号：US16839683

申请日：2020-04-03

Applicant: Infineon Technologies AG

Inventor： Christian Schweikert ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Waldemar Jakobi

IPC: H01L23/34 ,  H01L23/52 ,  H01L23/367 ,  G01K1/14 ,  H01L21/48

Abstract: A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.

公开(公告)号：US20240322697A1

公开(公告)日：2024-09-26

申请号：US18124223

申请日：2023-03-21

Applicant: Infineon Technologies AG

Inventor： Waldemar Jakobi ,  Christoph Koch ,  Tomas Manuel Reiter ,  Christian Schweikert

IPC: H02M3/335 ,  H01L23/495 ,  H02M7/00

CPC classification number: H02M3/33571 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49562 ,  H02M7/003

Abstract: A power semiconductor module includes: an electrically insulative frame; half bridge circuits housed in the electrically insulative frame, each half bridge circuit including one or more high-side power semiconductor dies and one or more low-side power semiconductor dies; a first structured metal frame embedded in the electrically insulative frame and electrically connected to a drain or collector terminal of the one or more high-side power semiconductor dies of each half bridge circuit; a second structured metal frame embedded in the electrically insulative frame and electrically connected to a source or emitter terminal of the one or more low-side power semiconductor dies of each half bridge circuit; and first openings in the electrically insulative frame that expose part of the first structured metal frame or part of the second structured metal frame at opposing first and second sidewalls of the electrically insulative frame and between adjacent ones of the half bridge circuits.

公开(公告)号：US10903158B2

公开(公告)日：2021-01-26

申请号：US16880664

申请日：2020-05-21

Applicant: Infineon Technologies AG

Inventor： Waldemar Jakobi ,  Christoph Koch

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L23/538 ,  H01L25/18 ,  H01L23/373

Abstract: A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks, and individual semiconductor chips each having a controllable semiconductor element, first and second load electrodes, and a control electrode. The first conductor track has a base section and further sections extending from the base section. The second conductor track has sections. The further sections of the first conductor track and the sections of the second conductor track extend parallel to one another in a first direction at least over a same lateral dimension of the individual semiconductor chips. The further sections of the first conductor track alternate with the sections of the second conductor track in a second direction orthogonal to the first direction. The individual semiconductor chips are arranged on the sections of the second conductor track. The first load electrodes are connected to the further sections of the first conductor track.

公开(公告)号：US20200286820A1

公开(公告)日：2020-09-10

申请号：US16880664

申请日：2020-05-21

Applicant: Infineon Technologies AG

Inventor： Waldemar Jakobi ,  Christoph Koch

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L23/538 ,  H01L25/18

Abstract: A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks, and individual semiconductor chips each having a controllable semiconductor element, first and second load electrodes, and a control electrode. The first conductor track has a base section and further sections extending from the base section. The second conductor track has sections. The further sections of the first conductor track and the sections of the second conductor track extend parallel to one another in a first direction at least over a same lateral dimension of the individual semiconductor chips. The further sections of the first conductor track alternate with the sections of the second conductor track in a second direction orthogonal to the first direction. The individual semiconductor chips are arranged on the sections of the second conductor track. The first load electrodes are connected to the further sections of the first conductor track.

公开(公告)号：US20200049569A1

公开(公告)日：2020-02-13

申请号：US16535381

申请日：2019-08-08

Applicant: Infineon Technologies AG

Inventor： Andre Arens ,  Waldemar Jakobi

IPC: G01K7/01 ,  H01L29/739 ,  H01L23/34 ,  H01L29/66 ,  H01L25/18 ,  H01L23/00 ,  H01L29/417 ,  H03K17/0812 ,  G01R19/14

Abstract: A power semiconductor circuit includes: a power semiconductor element having a gate electrode configured to actuate the power semiconductor element, a collector electrode, and an emitter electrode electrically connected to a first emitter terminal; and a temperature sensor having a first measurement point with a measurement terminal and a second measurement point electrically connected to the emitter electrode, so that a voltage which drops over the temperature sensor is measurable between the measurement terminal and the first emitter terminal for the temperature measurement. Corresponding methods for determining a temperature of a power semiconductor element and for determining a sign of a load current in a bridge circuit are also described.

公开(公告)号：US12211824B2

公开(公告)日：2025-01-28

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.