公开(公告)号：US20240363563A1

公开(公告)日：2024-10-31

申请号：US18766279

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming-Chyi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L23/4952 ,  H01L23/49866 ,  H01L23/53295 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/0558 ,  H01L2224/05686

Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

公开(公告)号：US20240321699A1

公开(公告)日：2024-09-26

申请号：US18733196

申请日：2024-06-04

Applicant: ROHM CO., LTD.

Inventor： Yo MOCHIZUKI ,  Kazunori FUJI

IPC: H01L23/495 ,  H01L23/10

CPC classification number: H01L23/49568 ,  H01L23/10 ,  H01L23/4952

Abstract: A semiconductor module includes a conductive member, a semiconductor element, and a heat transfer layer. The conductive member includes a first obverse surface facing in a thickness direction. The semiconductor element includes a first electrode and a first gate electrode that face the first obverse surface and a second electrode opposite to the side facing the first obverse surface. The first electrode connects to the conductive member. The heat transfer layer between the first obverse surface and the semiconductor element is conductively bonded to the first obverse surface, and connected to the first electrode. The heat transfer layer includes a first surface facing the first obverse surface and a second surface facing the semiconductor element. The second surface is spaced from the first gate electrode as viewed in the thickness direction. The second surface is surrounded by the periphery of the first surface as viewed in the thickness direction.

公开(公告)号：US12087673B2

公开(公告)日：2024-09-10

申请号：US17983249

申请日：2022-11-08

Applicant: Texas Instruments Incorporated

Inventor： Abram Castro ,  Usman Chaudhry ,  Joe Adam Garcia ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/67 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/67138 ,  H01L23/3121 ,  H01L23/49541 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3494 ,  H01L22/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/3511 ,  H05K2201/10636

Abstract: An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

公开(公告)号：US12066459B2

公开(公告)日：2024-08-20

申请号：US17364477

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Robert Allan Neidorff ,  Sreenivasan K Koduri

IPC: G01R1/067 ,  G01R31/28 ,  H01L23/495

CPC classification number: G01R1/06711 ,  G01R31/2851 ,  H01L23/4952

Abstract: A semiconductor device includes a leadframe having a first level and a second level. The semiconductor device includes a semiconductor die and a conductive alloy. The conductive alloy is between the semiconductor die and the first level of the lead frame. The conductive alloy is configured to be a current sense element. The semiconductor device further includes a first conductive post coupling the semiconductor die to the conductive alloy, a second conductive post coupling the semiconductor die to the conductive alloy, and a third conductive post coupling the semiconductor die to the second level of the lead frame. The second conductive post is configured to be a first sense terminal. The third conductive post is configured to be a second sense terminal.

公开(公告)号：US12062597B2

公开(公告)日：2024-08-13

申请号：US18297751

申请日：2023-04-10

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49527 ,  H01L23/49575

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

公开(公告)号：US20240186366A1

公开(公告)日：2024-06-06

申请号：US18522590

申请日：2023-11-29

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Kazumasa NISHIO ,  Kosei OSADA

IPC: H01L23/31 ,  H01L23/495

CPC classification number: H01L28/20 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49575 ,  H01L28/10

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and a substrate-side insulating layer disposed on the semiconductor substrate. The substrate-side insulating layer includes: a first oxide film; a second oxide film, disposed on the first oxide film and separated from the first oxide film; and a first nitride insulating layer and a second nitride insulating layer disposed between the first oxide film and the second oxide film. The second nitride insulating layer has a film density higher than a film density of the first nitride insulating layer.

公开(公告)号：US20240186224A1

公开(公告)日：2024-06-06

申请号：US18060680

申请日：2022-12-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro NISHIYAMA ,  Toshiyuki HATA ,  Tatsuaki TSUKUDA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49811 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/18 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/182

Abstract: Improving a performance of a semiconductor device. A method of manufacturing the semiconductor device, including steps of: forming a first convex portion on a front surface of a chip mounting portion; and mounting a semiconductor chip on the front surface of the chip mounting portion via a conductive adhesive material. Here, the semiconductor chip includes: a main transistor forming portion in which a main transistor is formed; and a sense transistor forming portion in which a sense transistor is formed. Also, in the step for mounting the semiconductor chip on the chip mounting portion, the semiconductor chip is mounted on the front surface of the chip mounting portion such that the sense transistor forming portion of the semiconductor chip overlaps the first convex portion formed on the front surface of the chip mounting portion in the step for forming the first convex portion.

公开(公告)号：US20240178111A1

公开(公告)日：2024-05-30

申请号：US18059465

申请日：2022-11-29

Applicant: NXP USA, INC.

Inventor： Chayathorn Saklang ,  Namrata Kanth ,  Stephen Ryan Hooper ,  Scott M. Hayes

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49593 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49555

Abstract: A method of manufacturing a semiconductor device with an attached battery is provided. The method includes affixing a semiconductor die to a die pad region of a first battery lead of a leadframe. The first battery lead of the leadframe is separated from a second battery lead of the leadframe. An encapsulant encapsulates the semiconductor die and portions of the first and second battery leads of the leadframe. The battery is affixed to an exposed portion of the first battery lead of the leadframe such that a first terminal of the battery is conductively connected to the first battery lead. An exposed portion of the second battery lead of the leadframe is bent to overlap a top surface portion of the battery such that a second terminal of the battery conductively connected to the second battery lead.

公开(公告)号：US20240178100A1

公开(公告)日：2024-05-30

申请号：US18464511

申请日：2023-09-11

Applicant: Mitsubishi Electric Corporation

Inventor： Naoki YOSHIMATSU ,  Shintaro ARAKI

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495

CPC classification number: H01L23/3736 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4924 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/45 ,  H01L2224/45124 ,  H01L2924/13055

Abstract: The semiconductor device includes: a heat spreader; a first solder layer; a second solder layer; a semiconductor element including a first surface bonded to the heat spreader through the first solder layer, a second surface facing the first surface, a first electrode disposed on the first surface, and a second electrode disposed on the second surface; a block bonded to the second electrode through the second solder layer; a sheet including a first portion, and a second portion having insulating properties and being in contact with the heat spreader; a first lead frame welded to the heat spreader; a second lead frame welded to the block; and a sealant having insulating properties and sealing the first and second lead frames, the heat spreader, the first and second solder layers, the semiconductor element, and the block.

公开(公告)号：US11996354B2

公开(公告)日：2024-05-28

申请号：US18298160

申请日：2023-04-10

Applicant: Rohm Co., Ltd.

Inventor： Koshun Saito ,  Hiroyuki Sakairi ,  Yasufumi Matsuoka ,  Kenichi Yoshimochi

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/48 ,  H01L2224/48245 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1067 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/30107

Abstract: A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.