公开(公告)号：US20040150056A1

公开(公告)日：2004-08-05

申请号：US10355726

申请日：2003-01-31

申请人： Infineon Technologies North America Corp ,  International Business Machines Corporation

发明人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

IPC分类号： H01L029/76 ,  H01L029/94

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/76838

摘要： A method of fabricating a semiconductor device having a dielectric structure on which a gate stack having a gate stack surface is formed, the gate stack having one or more gate metal layers comprising a gate metal, wherein the gate metal is recessed from the gate stack surface by a chemical etch, is provided. The method includes oxidizing the gate metal of the gate stack selectively to form a smooth side wall on the gate stack, and depositing a gate spacer to the gate stack.

摘要翻译： 一种制造具有电介质结构的半导体器件的方法，其上形成具有栅叠层表面的栅极叠层，所述栅叠层具有一个或多个包含栅极金属的栅极金属层，其中栅极金属从栅叠层表面凹陷 通过化学蚀刻。 所述方法包括选择性地氧化栅极堆叠的栅极金属，以在栅极堆叠上形成平滑的侧壁，以及将栅极间隔物沉积到栅极叠层。

公开(公告)号：US20040115921A1

公开(公告)日：2004-06-17

申请号：US10318606

申请日：2002-12-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Infineon Technologies North America Corp.

发明人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Staffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe JR. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

IPC分类号： H01L021/4763 ,  H01L021/44

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：US20040061190A1

公开(公告)日：2004-04-01

申请号：US10261218

申请日：2002-09-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Haining Yang

IPC分类号： H01L029/76

CPC分类号： H01L21/28247

摘要： As disclosed herein, an FEOL line conductor stack is formed including a base conductor layer, an overlying layer of tungsten, and an optional gate capping layer. The stack, including layers from the optional capping layer down to the base conductor layer are directionally etched until an underlying layer is exposed. Then, the substrate is exposed to one or the other or both of: 1) a silicon-containing ambient to form a self-aligned layer of tungsten silicide on sidewalls of the tungsten layer; and 2) a source of nitrogen to form a thin layer of tungsten nitride on sidewalls of the tungsten layer. Such tungsten silicide and/or tungsten nitride layers serves to protect the tungsten during subsequent processing, among which may include sidewall oxidation (e.g. for a polysilicon base conductor layer) and/or the forming of silicon nitride spacers on sidewalls of the gate stack.

摘要翻译： 如本文所公开的，形成FEOL线路导体堆叠，其包括基底导体层，钨的上覆层和可选的栅极覆盖层。 包括从可选的封盖层到底部导体层的层的堆叠被定向蚀刻直到暴露底层。 然后，将衬底暴露于以下之一或另一个或两者：1）含硅环境以在钨层的侧壁上形成硅化硅自对准层; 和2）氮源，以在钨层的侧壁上形成氮化钨薄层。 这种硅化钨和/或氮化钨层用于在随后的处理期间保护钨，其中可包括侧壁氧化（例如，用于多晶硅基底导体层）和/或在栅极堆叠的侧壁上形成氮化硅间隔物。