公开(公告)号：US20170302434A1

公开(公告)日：2017-10-19

申请号：US15249343

申请日：2016-08-26

申请人： Infinera Corporation

发明人： Vinod Narippatta ,  Mohammed Asad Rizvi

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04Q11/00 ,  H04J14/02 ,  H04L12/933

CPC分类号： H04L7/0075 ,  H04B10/50 ,  H04J3/1658 ,  H04J14/021 ,  H04L7/0331 ,  H04L49/15 ,  H04Q11/0003

摘要： Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.

公开(公告)号：US10331601B2

公开(公告)日：2019-06-25

申请号：US15249341

申请日：2016-08-26

申请人： Infinera Corporation

发明人： Vinod Narippatta ,  Unnikrishnan C V ,  Sanjay Kamat ,  Ashok Jain ,  Ashok Tatineni ,  Vishwanathan Paramasivam

IPC分类号： G06F13/40 ,  G06F13/16 ,  G11C7/10 ,  G06F12/02

摘要： Methods and apparatuses for data transformation are disclosed. An exemplary apparatus includes a first memory, a second memory, a cross-bar switch communicatively coupled between the first memory and the second memory, and a lookup table that specifies one or more memory addresses of the first memory to read out to the cross-bar switch, one or more memory addresses of the second memory to which to write data from the cross-bar switch, and a configuration of the cross-bar switch. An exemplary method includes determining, based on a lookup table, one or more memory addresses of a first memory to read out to a cross-bar switch, determining, based on the lookup table, one or more memory addresses of a second memory to which to write data from the cross-bar switch, and determining, based on the lookup table, a configuration of the cross-bar switch.

公开(公告)号：US09756406B1

公开(公告)日：2017-09-05

申请号：US15235834

申请日：2016-08-12

申请人： Infinera Corporation

发明人： Vinod Narippatta

IPC分类号： H04B10/00 ,  H04Q11/00 ,  G11C7/10 ,  H04J14/00

CPC分类号： H04Q11/0005 ,  H04Q2011/0016 ,  H04Q2011/0039 ,  H04Q2011/0045 ,  H04Q2011/0058

摘要： Systems, apparatus, and methods for a configurable gearbox with a variable number of input lanes and output lanes and a multiplexer for each output lane that can be configured to dynamically select any of the input lanes during each clock cycle.

公开(公告)号：US10103869B2

公开(公告)日：2018-10-16

申请号：US15249343

申请日：2016-08-26

申请人： Infinera Corporation

发明人： Vinod Narippatta ,  Mohammed Asad Rizvi

IPC分类号： H04Q11/00 ,  H04L7/00 ,  H04L7/033 ,  H04J14/02 ,  H04L12/933

摘要： Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.

公开(公告)号：US11996884B1

公开(公告)日：2024-05-28

申请号：US17527102

申请日：2021-11-15

申请人： Infinera Corporation

发明人： Vinod Narippatta ,  Ting-Kuang Chiang ,  Tulasi Veguru ,  Scott Pringle

IPC分类号： H04B10/079 ,  H04B10/40 ,  H04L49/90

CPC分类号： H04B10/0795 ,  H04B10/40 ,  H04L49/90

摘要： Systems, methods, devices, and other implementations for minimizing latency asymmetries and variations in a bi-directional link between two nodes in a communication system are described. To determine a variable latency for communication between two network nodes, a transmitting node can insert a line marker and a client marker into the data to be transmitted to the receiving node. The line marker and client marker can be inserted into the data at different portions or by different components of a transmitter. The receiving node can receive the transmitted data and extract the line marker and client marker. A delay associated with the line and client markers (Tc-TL) in the transmission device and a delay between the reception of the line and clien markers (Rc-RL) at the receiving node can be used to determine the variable latency.

公开(公告)号：US20230198622A1

公开(公告)日：2023-06-22

申请号：US17705057

申请日：2022-03-25

申请人： Infinera Corporation

发明人： Radhakrishna Valiveti ,  Rajan Rao ,  Vinod Narippatta ,  Sharfuddin Syed ,  Parthiban Kandappan

IPC分类号： H04B10/27

CPC分类号： H04B10/27

摘要： A method includes receiving client data; extracting overhead data from the client data; mapping the client data into one or more frames, where each of the one or more frames has a frame payload section and a frame overhead section, where the client data is mapped into the one or more frames; inserting the overhead data into the frame overhead section of the one or more frames; transporting the one or more frames across a network by generating a plurality of optical subcarriers carrying the one or more frames; extracting the overhead data from the frame overhead section of the one or more frames; recovering the client data from the one or more frames; inserting the extracted overhead data into the recovered client data to create modified client data; and outputting the modified client data.