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公开(公告)号：US20240371890A1
公开(公告)日：2024-11-07
申请号：US18628847
申请日：2024-04-08
Applicant: InnoLux Corporation
Inventor： Meng-Chang TSAI , Li-Jin Wang , Chan-Feng Chiu , Hsiao-Lan Su
Abstract: The present disclosure provides an electronic device, which includes a substrate, a first data line arranged on the substrate and extending along a first direction, a first electrode and a second electrode arranged on the substrate and arranged along the first direction, and a third electrode and a fourth electrode arranged on the substrate and arranged along the first direction, the first electrode, the second electrode, the third electrode and the fourth electrode are electrically connected with the first data line, and the first electrode and the second electrode are located on a first side of the first data line, and the third electrode and the fourth electrode are located on a second side of the first data line relative to the first side.
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公开(公告)号：US12190839B2
公开(公告)日：2025-01-07
申请号：US18373977
申请日：2023-09-28
Applicant: InnoLux Corporation
Inventor： Yeh-Yi Lan , Cheng-Cheng Pan , Ming-Chin Hsu , Hsiu-Chuan Chung , Szu-Fan Wu , Chien-Hung Chan , Huang-Chi Chao , Wai Lon Chan , Yao-Lien Hsieh , Li-Jin Wang
IPC: G09G3/36
Abstract: An electronic device includes gate lines, maintained at a low level voltage during a blank period and sequentially scanned during an active period in a frame period, and data lines. Voltage polarities of the data lines for all the blank period are respectively identical with voltage polarities of the data lines during the active period. A first level voltage applied to one of the data lines during all the blank period is related to an average value or a maximum value of level voltages of a portion or all of the data lines during the active period. A time length of the blank period in the frame period with the average value or the maximum value applied to one of the data lines during all the blank period is longer than a first time length of a first blank period in a first frame period adjacent to the frame period.
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公开(公告)号：US20240312393A1
公开(公告)日：2024-09-19
申请号：US18669548
申请日：2024-05-21
Applicant: Innolux Corporation
Inventor： Chan-Feng Chiu , Ming-Feng Hsieh , Li-Jin Wang , Meng-Chang Tsai
CPC classification number: G09G3/2092 , G09G3/3614 , G09G3/3648 , G09G2300/0426 , G09G2310/0205 , G09G2310/0267 , G09G2310/0275
Abstract: An electronic device includes a first substrate; a first pixel electrode, a second pixel electrode and a third pixel electrode disposed on the first substrate along a first direction; and a first metal element, a second metal element and a third metal element disposed on the first substrate along the first direction. A projection of the first metal element and a projection of the second metal element are disposed between a projection of the first pixel electrode and a projection of the second pixel electrode. A projection of the third metal element is disposed between the projection of the second pixel electrode and a projection of the third pixel electrode. A first width between a outer edge of the first metal element and a outer edge of the second metal element is greater than a second width of the third metal element.
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Patent Agency Ranking
公开(公告)号：US20240021170A1
公开(公告)日：2024-01-18
申请号：US18373977
申请日：2023-09-28
Applicant: InnoLux Corporation
Inventor： Yeh-Yi LAN , Cheng-Cheng PAN , Ming-Chin HSU , Hsiu-Chuan CHUNG , Szu-Fan WU , Chien-Hung CHAN , Huang-Chi CHAO , Wai Lon CHAN , Yao-Lien HSIEH , Li-Jin Wang
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G2310/061 , G09G2310/0275 , G09G2320/0247 , G09G2340/0435 , G09G2310/08
Abstract: An electronic device includes gate lines, maintained at a low level voltage during a blank period and sequentially scanned during an active period in a frame period, and data lines. Voltage polarities of the data lines for all the blank period are respectively identical with voltage polarities of the data lines during the active period. A first level voltage applied to one of the data lines during all the blank period is related to an average value or a maximum value of level voltages of a portion or all of the data lines during the active period. A time length of the blank period in the frame period with the average value or the maximum value applied to one of the data lines during all the blank period is longer than a first time length of a first blank period in a first frame period adjacent to the frame period.
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公开(公告)号：US10043436B2
公开(公告)日：2018-08-07
申请号：US15184561
申请日：2016-06-16
Applicant: InnoLux Corporation
Inventor： Li-Jin Wang , Yao-Lien Hsieh , Chan-Feng Chiu , Chung-Yi Wang
IPC: G09G3/20
Abstract: A display device including a first pixel, a second pixel, and a control unit is provided. The first and second pixels are coupled to a data line. The control unit generates a first original image signal and a second original image signal required by the first and second pixels in a frame time according to an analog image and generates a first output image signal and a second output image signal according to the difference between the first and second original image signals. In the frame time, the control unit sequentially provides the first and second output image signals to the first and second pixels via the data line.
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公开(公告)号：US12027096B2
公开(公告)日：2024-07-02
申请号：US18077199
申请日：2022-12-07
Applicant: Innolux Corporation
Inventor： Chan-Feng Chiu , Ming-Feng Hsieh , Li-Jin Wang , Meng-Chang Tsai
CPC classification number: G09G3/2092 , G09G3/3614 , G09G3/3648 , G09G2300/0426 , G09G2310/0205 , G09G2310/0267 , G09G2310/0275
Abstract: An electronic device includes an array substrate. The array substrate includes first to third gate lines, a first to third pixel units, and a gate driving circuit. The third gate line is disposed between the first and second gate lines. The first pixel unit is electrically connected to the first gate line and the data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driving circuit is electrically connected to the first to third gate lines. The gate driving circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.
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公开(公告)号：US20230222956A1
公开(公告)日：2023-07-13
申请号：US18077199
申请日：2022-12-07
Applicant: Innolux Corporation
Inventor： Chan-Feng Chiu , Ming-Feng Hsieh , Li-Jin Wang , Meng-Chang Tsai
CPC classification number: G09G3/2092 , H01L27/124 , G09G2310/0267 , G09G2310/0275
Abstract: An electronic device includes an array substrate. The array substrate includes first to third gate lines, a first to third pixel units, and a gate driving circuit. The third gate line is disposed between the first and second gate lines. The first pixel unit is electrically connected to the first gate line and the data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driving circuit is electrically connected to the first to third gate lines. The gate driving circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.
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公开(公告)号：US20220130317A1
公开(公告)日：2022-04-28
申请号：US17482430
申请日：2021-09-23
Applicant: InnoLux Corporation
Inventor： Yeh-Yi LAN , Cheng-Cheng PAN , Ming-Chin HSU , Hsiu-Chuan CHUNG , Szu-Fan WU , Chien-Hung CHAN , Huang-Chi CHAO , Wai Lon CHAN , Yao-Lien HSIEH , Li-Jin Wang
IPC: G09G3/20
Abstract: The present disclosure provides an electronic device and an electronic device driving method. The electronic device includes a plurality of gate lines and a plurality of data lines. The plurality of gate lines are sequentially scanned during an active period in a frame period, and the plurality of gate lines are maintained at a low level voltage during a blank period in the frame period. Voltage polarities of the plurality of data lines during a first time period of the blank period are respectively identical with voltage polarities of the plurality of data lines during the active period.
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