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公开(公告)号：US10749732B2
公开(公告)日：2020-08-18
申请号：US16775130
申请日：2020-01-28
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Jitendra Swarnkar , Michael Duckering , Andre Sczapanek , Scott Feller , Shaun Lytollis
IPC: H04L29/08 , G06F11/20 , H04L12/427 , H04L1/22 , H04L12/26 , H04L12/40 , H04W28/06 , H04W28/04 , H04L12/24
Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.
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公开(公告)号：US10009214B1
公开(公告)日：2018-06-26
申请号：US15673352
申请日：2017-08-09
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Jitendra Swarnkar , Michael Duckering , Andre Sczapanek , Scott Feller , Shaun Lytollis
IPC: H03D1/04 , H04L29/08 , G06F11/20 , H04L12/427 , H04L1/22 , H04L12/24 , H04L12/40 , H04W28/06 , H04W28/04
Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.
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公开(公告)号：US11121955B2
公开(公告)日：2021-09-14
申请号：US16848597
申请日：2020-04-14
Applicant: INPHI CORPORATION
Inventor： Jamal Riani , Arash Farhoodfar , Sudeep Bhoja , Tarun Setya
Abstract: A data communication device includes a host receive section for receiving incoming host data from a host device. The host receive section includes a plurality of host receive lanes. A host transmit section for transmitting outgoing host data to the host device includes a plurality of host transmit lanes and a host cross point section. A line receive section for receiving incoming line data from a line device includes a plurality of line receive lanes. A line transmit section for transmitting outing line data to the line device includes a plurality of line transmit lanes and a line cross point section. A link monitor section coupled to the host transmit section and the line receive section is configured to detect errors between the host transmit section and the line receive section.
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公开(公告)号：US10659337B2
公开(公告)日：2020-05-19
申请号：US16115291
申请日：2018-08-28
Applicant: INPHI CORPORATION
Inventor： Jamal Riani , Arash Farhoodfar , Sudeep Bhoja , Tarun Setya
Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.
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公开(公告)号：US10601449B2
公开(公告)日：2020-03-24
申请号：US16575236
申请日：2019-09-18
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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Patent Agency Ranking
公开(公告)号：US10374750B2
公开(公告)日：2019-08-06
申请号：US16155610
申请日：2018-10-09
Applicant: INPHI CORPORATION
Inventor： Benjamin P. Smith , Arash Farhoodfar
IPC: H04L1/00 , H03M13/29 , H04B10/50 , H04B10/54 , H04B10/69 , H04B10/516 , H04B10/532
Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.
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公开(公告)号：US10320425B2
公开(公告)日：2019-06-11
申请号：US15194432
申请日：2016-06-27
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Frank R. Kschischang , Andrew Hunt , Benjamin P. Smith , John Lodge
Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code. Thus, each row in [Bi−1T Bi] and each column in [ B i B i + 1 T ] , for example, is a valid codeword.
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公开(公告)号：US10236994B2
公开(公告)日：2019-03-19
申请号：US15836603
申请日：2017-12-08
Applicant: INPHI CORPORATION
Inventor： Benjamin P. Smith , Jamal Riani , Sudeep Bhoja , Arash Farhoodfar , Vipul Bhatt
IPC: H04B10/69 , H04B10/58 , H04B10/2507 , H04B10/516 , H04B10/00
Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
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公开(公告)号：US10236907B2
公开(公告)日：2019-03-19
申请号：US15981844
申请日：2018-05-16
Applicant: INPHI CORPORATION
Inventor： Andre Szczepanek , Arash Farhoodfar , Sudeep Bhoja , Sean Batty , Shaun Lytollis
Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).
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公开(公告)号：US10033410B2
公开(公告)日：2018-07-24
申请号：US15206011
申请日：2016-07-08
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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