公开(公告)号：US09794087B2

公开(公告)日：2017-10-17

申请号：US15059609

申请日：2016-03-03

Applicant: Integrated Device Technology, Inc.

Inventor： Yue Yu ,  Craig DeSimone ,  Al Xuefeng Fang ,  Yanbo Wang

IPC: H04L25/02 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4093 ,  G06F13/40

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

公开(公告)号：US10171268B2

公开(公告)日：2019-01-01

申请号：US15698867

申请日：2017-09-08

Applicant: Integrated Device Technology, Inc.

Inventor： Yue Yu ,  Craig DeSimone ,  Al Xuefeng Fang ,  Yanbo Wang

IPC: H04L25/02 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50 ,  G06F13/40

Abstract: An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.

公开(公告)号：US20170256303A1

公开(公告)日：2017-09-07

申请号：US15059609

申请日：2016-03-03

Applicant: Integrated Device Technology, Inc.

Inventor： Yue Yu ,  Craig DeSimone ,  Al Xuefeng Fang ,  Yanbo Wang

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

公开(公告)号：US20170373886A1

公开(公告)日：2017-12-28

申请号：US15698867

申请日：2017-09-08

Applicant: Integrated Device Technology, Inc.

Inventor： Yue Yu ,  Craig DeSimone ,  Al Xuefeng Fang ,  Yanbo Wang

IPC: H04L25/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4094 ,  G06F13/40

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.