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公开(公告)号：US11126218B2
公开(公告)日：2021-09-21
申请号：US16520635
申请日：2019-07-24
摘要： A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.
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公开(公告)号：US11372441B2
公开(公告)日：2022-06-28
申请号：US16521217
申请日：2019-07-24
摘要： A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.
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公开(公告)号：US20200033910A1
公开(公告)日：2020-01-30
申请号：US16520635
申请日：2019-07-24
摘要： A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.
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公开(公告)号：US20200033909A1
公开(公告)日：2020-01-30
申请号：US16521217
申请日：2019-07-24
摘要： A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.
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