公开(公告)号：US09479182B1

公开(公告)日：2016-10-25

申请号：US14975388

申请日：2015-12-18

Applicant: Integrated Device Technology, Inc.

Inventor： Zaher Baidas ,  Bogdan Staicu ,  Menno Tjeerd Spijker

IPC: H03L7/08 ,  H03L7/083

CPC classification number: H03L7/07 ,  H03L7/08 ,  H04L7/033

Abstract: A method of synchronizing operations between integrated circuits can include transmitting a first clock signal from a first transmitter associated with a first integrated circuit of a first system, to a receiver associated with a second integrated circuit of a second system, receiving a second clock signal from a second transmitter associated with a third integrated circuit of the second system, receiving at the first system a first phase difference determined by the second system, wherein the first phase difference is determined between the first clock signal at the second system and the second clock signal at the second system, determining a second phase difference at the first system, wherein the second phase difference is determined between the first clock signal at the first system and the second clock signal at the first system, and determining a difference between the first phase difference and the second phase difference.

Abstract translation: 在集成电路之间同步操作的方法可以包括将与第一系统的第一集成电路相关联的第一发射机的第一时钟信号传输到与第二系统的第二集成电路相关联的接收机，从第二系统接收第二时钟信号 与所述第二系统的第三集成电路相关联的第二发射机，在所述第一系统处接收由所述第二系统确定的第一相位差，其中在所述第二系统处的所述第一时钟信号和所述第二时钟信号之间确定所述第一相位差 在第二系统中，确定第一系统处的第二相位差，其中在第一系统处的第一时钟信号和第一系统的第二时钟信号之间确定第二相位差，并且确定第一相位差 和第二相位差。

公开(公告)号：US11126218B2

公开(公告)日：2021-09-21

申请号：US16520635

申请日：2019-07-24

Applicant: Integrated Device Technology, Inc.

Inventor： Zaher Baidas ,  Ernst JG den Broeder ,  Leonid Goldin

IPC: G06F1/12 ,  G06F1/10 ,  G06F13/42 ,  H04B14/02 ,  G06F1/14

Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

公开(公告)号：US20200033910A1

公开(公告)日：2020-01-30

申请号：US16520635

申请日：2019-07-24

Applicant: Integrated Device Technology, Inc.

Inventor： Zaher Baidas ,  Ernst JG den Broeder ,  Leonid Goldin

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/14 ,  H04B14/02 ,  G06F13/42

Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

公开(公告)号：US10075284B1

公开(公告)日：2018-09-11

申请号：US15364602

申请日：2016-11-30

Applicant: Integrated Device Technology, Inc.

Inventor： Silvana Rodrigues ,  Michael Rupert ,  Zaher Baidas ,  Leon Goldin

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/49 ,  H04L12/935

CPC classification number: H04L7/033 ,  H04J3/0688 ,  H04J3/0697 ,  H04L25/4902 ,  H04L49/30

Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

公开(公告)号：US09628255B1

公开(公告)日：2017-04-18

申请号：US14975226

申请日：2015-12-18

Applicant: Integrated Device Technology, Inc.

Inventor： Zaher Baidas ,  Bogdan Staicu ,  Menno Tjeerd Spijker

IPC: H04L7/00

CPC classification number: H04L5/00 ,  H04L7/0008 ,  H04L25/49

Abstract: A method of operating a clock circuit can include transmitting a clock signal from a transmitter of a first system to a receiver of a second system, where a first repeating edge of a clock cycle of the clock signal repeats at a predetermined constant frequency within the clock signal to synchronize operations of the second system, and varying, by the first system, a second edge within the clock cycle of the clock signal to transmit a data transmission within the clock signal.