公开(公告)号：US20210279061A1

公开(公告)日：2021-09-09

申请号：US17323409

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F9/32

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

公开(公告)号：US20190129721A1

公开(公告)日：2019-05-02

申请号：US16233955

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F9/32

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

公开(公告)号：US20170206087A1

公开(公告)日：2017-07-20

申请号：US15478520

申请日：2017-04-04

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/3016 ,  G06F9/325

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

公开(公告)号：US20170075691A1

公开(公告)日：2017-03-16

申请号：US15363785

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/355 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3555 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/355 ,  G06F9/3802 ,  G06F9/3893

Abstract: An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.

Abstract translation: 描述了具有功能单元逻辑电路的装置。 功能单元逻辑电路具有第一寄存器以存储具有用于多维数据结构的每个维度的元素的第一输入向量操作数。 第一个向量操作数的每个元素指定其相应维度的大小。 功能单元具有第二寄存器，用于存储指定多维结构的特定段的坐标的第二输入向量操作数。 功能单元还具有逻辑电路，用于相对于多维结构的原点片段的地址计算特定片段的地址偏移。

公开(公告)号：US20180373538A1

公开(公告)日：2018-12-27

申请号：US16120983

申请日：2018-09-04

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F9/32

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

公开(公告)号：US20170052783A1

公开(公告)日：2017-02-23

申请号：US15346531

申请日：2016-11-08

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  BRET L. TOLL ,  JESUS CORBAL

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036

Abstract: A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

Abstract translation: 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。