公开(公告)号：US20220100569A1

公开(公告)日：2022-03-31

申请号：US17033739

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： DAEHO SEO ,  VIKASH AGARWAL ,  JOHN ESPER ,  KHARY ALEXANDER ,  ASAVARI PARANJAPE ,  JONATHAN COMBS

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54

Abstract: Systems, methods, and apparatuses relating to circuitry to implement scalable port-binding for asymmetric execution ports and allocation widths of a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into sets of one or more micro-operations, an instruction decode queue to store the sets of one or more micro-operations, a plurality of different types of execution circuits that each comprise a respective input port and a respective input queue, and an allocation circuit comprising a plurality of allocation lanes coupled to the instruction decode queue and to the input ports of the plurality of different types of execution circuits, wherein the allocation circuit is to, for an input of micro-operations on the plurality of allocation lanes, generate a sorted list of occupancy of the input queues of each input port, generate a pre-binding mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes in a circular order according to the sorted list, when a type of micro-operation from an allocation lane does not match a type of execution circuit of an input port in the pre-binding mapping, slide the pre-binding mapping so that the input port maps to a next allocation lane having a matching type of micro-operation to generate a final mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes, and bind the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes according to the final mapping.

公开(公告)号：US20220308882A1

公开(公告)日：2022-09-29

申请号：US17214823

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： JONATHAN COMBS ,  MICHAEL CHYNOWETH ,  BEEMAN STRONG ,  CHARLIE HEWETT ,  PATRICK KONSOR ,  VIDISHA CHIRRA ,  ASAVARI PARANJAPE ,  AHMAD YASIN

IPC: G06F9/38 ,  G06F12/0802 ,  G06F11/30 ,  G06F11/34

Abstract: Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.