公开(公告)号：US09251095B2

公开(公告)日：2016-02-02

申请号：US14339756

申请日：2014-07-24

Applicant: Intel Corporation

Inventor： David Champagne ,  Abhishek Tiwari ,  Wei Wu ,  Christopher J. Hughes ,  Sanjeev Kumar ,  Shih-Lien Lu

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/681

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

公开(公告)号：US20140337600A1

公开(公告)日：2014-11-13

申请号：US14339756

申请日：2014-07-24

Applicant: Intel Corporation

Inventor： David Champagne ,  Abhishek Tiwari ,  Wei Wu ,  Christopher J. Hughes ,  Sanjeev Kumar ,  Shih-Lien Lu

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/681

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括翻译后备缓冲器（TLB），用于存储每个具有翻译部分以存储虚拟地址（VA）至物理地址（PA）转换）的条目，以及存储用于存储器的位的第二部分 与VA到PA转换相关联的页面，其中位指示存储器页面中的信息的属性。 描述和要求保护其他实施例。