公开(公告)号：US20250120143A1

公开(公告)日：2025-04-10

申请号：US18482192

申请日：2023-10-06

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Adam Brand ,  Chen-Guan Lee ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Adithya Shankar ,  Marko Radosavljevic

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in devices that include CFETs, either by implementing the extended drain transistor across both CFET layers, or by providing a sub-fin pedestal with the well regions in the lower layer.