公开(公告)号：US20180181396A1

公开(公告)日：2018-06-28

申请号：US15391789

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Alexander Y. OSTANEVICH ,  Sergey P. SCHERBININ ,  Jayesh IYER ,  Dmitry M. MASLENNIKOV ,  Denis G. MOTIN ,  Alexander V. ERMOLOVICH ,  Andrey CHUDNOVETS ,  Sergey A. ROZHKOV ,  Boris A. BABAYAN

IPC: G06F9/30

CPC classification number: G06F9/30087 ,  G06F9/30 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/38 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3859

Abstract: An apparatus includes a binary translator to hoist a load instruction in a branch of a conditional statement above the conditional statement and insert a speculation control of load (SCL) instruction in a complementary branch of the conditional statement, where the SCL instruction provides an indication of a real program order (RPO) of the load instruction before the load instruction was hoisted. The apparatus further includes an execution circuit to execute the load instruction to perform a load and cause an entry for the load instruction to be inserted in an ordering buffer, and where the execution circuit is to execute the SCL instruction to locate the entry for the load instruction in the ordering buffer using the RPO of the load instruction provided by the SCL instruction and discard the entry for the load instruction from the ordering buffer.

公开(公告)号：US20180181405A1

公开(公告)日：2018-06-28

申请号：US15390194

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jayesh IYER ,  Sergey P. SCHERBININ ,  Alexander Y. OSTANEVICH ,  Dmitry M. MASLENNIKOV ,  Denis G. MOTIN ,  Alexander V. ERMOLOVICH ,  Andrey CHUDNOVETS ,  Sergey A. ROZHKOV ,  Boris A. BABAYAN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F8/445 ,  G06F8/4452 ,  G06F8/452 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/3009 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30127 ,  G06F9/30138 ,  G06F9/30141 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/381 ,  G06F9/384 ,  G06F9/3851

Abstract: An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.

公开(公告)号：US20180181397A1

公开(公告)日：2018-06-28

申请号：US15391791

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Alexander Y. OSTANEVICH ,  Jayesh IYER ,  Sergey P. SCHERBININ ,  Dmitry M. MASLENNIKOV ,  Denis G. MOTIN ,  Alexander V. ERMOLOVICH ,  Andrey CHUDNOVETS ,  Sergey A. ROZHKOV ,  Boris A. BABAYAN

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30021 ,  G06F9/3005 ,  G06F9/30072 ,  G06F9/3851 ,  G06F9/3855

Abstract: An apparatus includes a first circuit to determine a real program order (RPO) of an eldest undispatched instruction from among a plurality of strands, a second circuit to determine an RPO limit based on a delta value and the RPO of the eldest undispatched instruction, an ordering buffer to store entries for instructions that are waiting to be retired, and a third circuit to execute an orderable instruction from a strand from the plurality of strands to cause an entry for the orderable instruction to be inserted into the ordering buffer in response to a determination that an RPO of the orderable instruction is less than or equal to the RPO limit.