公开(公告)号：US11210094B2

公开(公告)日：2021-12-28

申请号：US16585427

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/38 ,  G06F9/50 ,  G06T1/20 ,  G06F9/30 ,  G06F12/0815 ,  G06F8/41

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US20220156068A1

公开(公告)日：2022-05-19

申请号：US17530040

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0815 ,  G06F9/50

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US20210096855A1

公开(公告)日：2021-04-01

申请号：US16585427

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0815

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.