公开(公告)号：US11210094B2

公开(公告)日：2021-12-28

申请号：US16585427

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/38 ,  G06F9/50 ,  G06T1/20 ,  G06F9/30 ,  G06F12/0815 ,  G06F8/41

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US20230195503A1

公开(公告)日：2023-06-22

申请号：US17553359

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Michael Cole ,  Pattabhiraman K ,  Ankita A. Agarwal

IPC: G06F9/46

CPC classification number: G06F9/466

Abstract: Methods, systems and apparatuses may provide for technology that includes configuration registers to maintain state information, a filter coupled to the configuration registers, the filter to extract transactions of interest from a plurality of incoming transactions based on the state information, wherein the transactions of interest are extracted on a transaction-by-transaction basis, a first hardware path coupled to the filter, the first hardware path to generate a count of the transactions of interest on a cycle-by-cycle basis, a second hardware path coupled to the filter, the second hardware path to measure a total latency of the transactions of interest on the cycle-by-cycle basis, and an output interface coupled to the first hardware path and the second hardware path, the output interface to determine an average latency of the transactions of interest based on the count of the transactions of interest and the total latency of the transactions of interest.

公开(公告)号：US20220156068A1

公开(公告)日：2022-05-19

申请号：US17530040

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0815 ,  G06F9/50

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US20210096855A1

公开(公告)日：2021-04-01

申请号：US16585427

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0815

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.