公开(公告)号：US20250133811A1

公开(公告)日：2025-04-24

申请号：US19000050

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Christine RADLINGER ,  Tongtawee WACHARASINDHU ,  Andre BARAN ,  Kiran CHIKKADI ,  Devin MERRILL ,  Nilesh DENDGE ,  David J. TOWNER ,  Christopher KENYON

IPC: H10D64/68 ,  H10D64/27 ,  H10D84/83

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.

公开(公告)号：US20240347618A1

公开(公告)日：2024-10-17

申请号：US18755189

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Christine RADLINGER ,  Tongtawee WACHARASINDHU ,  Andre BARAN ,  Kiran CHIKKADI ,  Devin MERRILL ,  Nilesh DENDGE ,  David J. TOWNER ,  Christopher KENYON

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/517 ,  H01L27/0886 ,  H01L29/42364

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.