公开(公告)号：US20240427600A1

公开(公告)日：2024-12-26

申请号：US18827453

申请日：2024-09-06

Applicant: Intel Corporation

Inventor： Robert C. VALENTINE ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Robert D. CAVIN ,  Bret L. TOLL ,  Santiago Galan DURAN ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Edward Thomas GROCHOWSKI ,  Jonathan Cannon HALL ,  Dennis R. BRADFORD ,  Elmoustapha OULD-AHMED-VALL ,  James C ABEL ,  Mark CHARNEY ,  Seth ABRAHAM ,  Suleyman SAIR ,  Andrew Thomas FORSYTH ,  Lisa WU ,  Charles YOUNT

IPC: G06F9/30 ,  G06F9/34 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US20240061683A1

公开(公告)日：2024-02-22

申请号：US18239106

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Robert C. VALENTINE ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Robert D. CAVIN ,  Bret L. TOLL ,  Santiago Galan DURAN ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Edward Thomas GROCHOWSKI ,  Jonathan Cannon HALL ,  Dennis R. BRADFORD ,  Elmoustapha OULD-AHMED-VALL ,  James C ABEL ,  Mark CHARNEY ,  Seth ABRAHAM ,  Suleyman SAIR ,  Andrew Thomas FORSYTH ,  Lisa WU ,  Charles YOUNT

IPC: G06F9/30 ,  G06F9/34 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696 ,  G06F9/30018 ,  H01L29/66

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US20240420273A1

公开(公告)日：2024-12-19

申请号：US18211152

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Andrew Thomas FORSYTH

IPC: G06T1/20 ,  G06F9/30

Abstract: A system that includes a graphics processing unit (GPU) that includes at least one processor and multiple registers. In some examples, based on execution of an instruction by at least one of the at least one processor to allocate a particular number of registers to a thread, assign the number of registers to the thread. In some examples, a compiler is to consider register demands for a code segment and number of available registers in determining a number of registers to allocate to the code segment.

公开(公告)号：US20190108030A1

公开(公告)日：2019-04-11

申请号：US16145160

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Jesus CORBAL SAN ADRIAN ,  Bret L. TOLL ,  Robert C. VALENTINE ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Andrew Thomas FORSYTH ,  Elmoustapha OULD-AHMED-VALL ,  Dennis R. BRADFORD ,  Lisa K. WU

IPC: G06F9/30

Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.

公开(公告)号：US20220129274A1

公开(公告)日：2022-04-28

申请号：US17524624

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Robert C. VALENTINE ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Robert D. CAVIN ,  Bret L. TOLL ,  Santiago Galan DURAN ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Edward Thomas GROCHOWSKI ,  Jonathan Cannon HALL ,  Dennis R. BRADFORD ,  Elmoustapha OULD-AHMED-VALL ,  James C ABEL ,  Mark CHARNEY ,  Seth ABRAHAM ,  Suleyman SAIR ,  Andrew Thomas FORSYTH ,  Lisa WU ,  Charles YOUNT

IPC: G06F9/30 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US20190227800A1

公开(公告)日：2019-07-25

申请号：US16289506

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Robert C. VALENTINE ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Robert D. CAVIN ,  Bret L. TOLL ,  Santiago Galan DURAN ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Edward Thomas GROCHOWSKI ,  Jonathan Cannon HALL ,  Dennis R. BRADFORD ,  Elmoustapha OULD-AHMED-VALL ,  James C. ABEL ,  Mark CHARNEY ,  Seth ABRAHAM ,  Suleyman SAIR ,  Andrew Thomas FORSYTH ,  Lisa WU ,  Charles YOUNT

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US20190108029A1

公开(公告)日：2019-04-11

申请号：US16145156

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Jesus CORBAL SAN ADRIAN ,  Bret L. TOLL ,  Robert C. VALENTINE ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Andrew Thomas FORSYTH ,  Elmoustapha OULD-AHMED-VALL ,  Dennis R. BRADFORD ,  Lisa K. WU

IPC: G06F9/30

Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.