公开(公告)号：US20230342035A1

公开(公告)日：2023-10-26

申请号：US18215907

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Todd A. HINCK ,  Archhana M

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0644 ,  G06F3/0673

Abstract: Bandwidth efficiency is improved by reducing time to access a cache line in a DRAM chip. A memory array in the DRAM chip is internally segmented into two equal size portions, each portion having a plurality of banks. Each respective portion is internally segmented into two equal size sub-portions. A cache line in the memory array is accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time.