公开(公告)号：US20230342035A1

公开(公告)日：2023-10-26

申请号：US18215907

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Todd A. HINCK ,  Archhana M

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0644 ,  G06F3/0673

Abstract: Bandwidth efficiency is improved by reducing time to access a cache line in a DRAM chip. A memory array in the DRAM chip is internally segmented into two equal size portions, each portion having a plurality of banks. Each respective portion is internally segmented into two equal size sub-portions. A cache line in the memory array is accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time.

公开(公告)号：US20240080988A1

公开(公告)日：2024-03-07

申请号：US18506951

申请日：2023-11-10

Applicant: Intel Corporation

Inventor： Todd A. HINCK ,  Michael T. CROCKER ,  Xiang LI ,  Vijaya K. BODDU

IPC: H05K1/18 ,  H05K1/02 ,  H05K7/14

CPC classification number: H05K1/181 ,  H05K1/0209 ,  H05K7/1429 ,  H05K2201/10159 ,  H05K2201/10378

Abstract: A system includes a processor, such as a CPU, surrounded by high-density memory with lower profile than a standard DIMM. The low profile, high-density memory provides multiple memory channels for the processor. With the memory configuration, the system can maintain the memory configurability with increased density and increased memory channels for the processor.

公开(公告)号：US20230393740A1

公开(公告)日：2023-12-07

申请号：US18235709

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Todd A. HINCK ,  Kuljit S. BAINS

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0626 ,  G06F3/0644 ,  G06F3/0673

Abstract: Four-way pseudo split Dynamic Random Access Memory (DRAM) architectures and techniques are described. In one example, a 4-way pseudo split DRAM device includes four slices. In one example, a memory channel includes four pseudo channels, each of the four pseudo channels includes a corresponding slice of each of the plurality of DRAM devices. In one example, each of the four pseudo channels includes one slice from each of the plurality of DRAM devices.