公开(公告)号：US20200342946A1

公开(公告)日：2020-10-29

申请号：US16396478

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Han ZHAO ,  Richard FASTOW ,  Krishna K. PARAT ,  Arun THATHACHARY ,  Narayanan RAMANAN

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08

Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

公开(公告)号：US20220366991A1

公开(公告)日：2022-11-17

申请号：US17321114

申请日：2021-05-14

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Tarek Ahmed AMEEN BESHARI ,  Matin AMANI ,  Narayanan RAMANAN ,  Arun THATHACHARY

IPC: G11C16/34 ,  G06F3/06

Abstract: An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.