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公开(公告)号：US20220293194A1
公开(公告)日：2022-09-15
申请号：US17202137
申请日：2021-03-15
Applicant: Intel Corporation
Inventor： Narayanan RAMANAN
Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
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公开(公告)号：US20220293193A1
公开(公告)日：2022-09-15
申请号：US17202133
申请日：2021-03-15
Applicant: Intel Corporation
Inventor： Narayanan RAMANAN
Abstract: Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.
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Patent Agency Ranking
公开(公告)号：US20220172784A1
公开(公告)日：2022-06-02
申请号：US17107679
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Shantanu R. RAJWADE , Bayan NASRI , Tzu-Ning FANG , Rezaul HAQUE , Dhanashree R. KULKARNI , Narayanan RAMANAN , Matin AMANI , Ahsanur RAHMAN , Seong Je PARK , Netra MAHULI
Abstract: A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.
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公开(公告)号：US20200342946A1
公开(公告)日：2020-10-29
申请号：US16396478
申请日：2019-04-26
Applicant: Intel Corporation
Inventor： Han ZHAO , Richard FASTOW , Krishna K. PARAT , Arun THATHACHARY , Narayanan RAMANAN
Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.
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5.发明申请公开(公告)号：US20220366991A1
公开(公告)日：2022-11-17
申请号：US17321114
申请日：2021-05-14
Applicant: Intel Corporation
Inventor： Shantanu R. RAJWADE , Tarek Ahmed AMEEN BESHARI , Matin AMANI , Narayanan RAMANAN , Arun THATHACHARY
Abstract: An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.
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6.发明申请公开(公告)号：US20220208286A1
公开(公告)日：2022-06-30
申请号：US17134010
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Tarek Ahmed AMEEN BESHARI , Shantanu R. RAJWADE , Matin AMANI , Narayanan RAMANAN
Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.
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公开(公告)号：US20220084606A1
公开(公告)日：2022-03-17
申请号：US17023094
申请日：2020-09-16
Applicant: Intel Corporation
Inventor： Xiang YANG , Guangyu HUANG , Narayanan RAMANAN , Pranav KALAVADE , Ali KHAKIFIROOZ
Abstract: A method is described. The method includes programming a column of flash storage cells in a direction along the column in which a parasitic transistor that resides between a cell being programmed and an immediately next cell to be programmed has lower resistivity as compared to a corresponding parasitic transistor that exists if the programming were to be performed in an opposite direction along the column.
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