公开(公告)号：US20250112160A1

公开(公告)日：2025-04-03

申请号：US18374611

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Andrew P. COLLINS ,  Jian Yong XIE ,  Aruna KUMAR ,  Rinkle JAIN ,  Basavaraj KANTHI

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: Embodiments disclosed herein include an apparatus for bump translation. In an embodiment, the apparatus includes a substrate with a first bump field with a first height and a first depth on the substrate, where the first depth is orthogonal to the first height, and where the first bump field further comprises a first pitch in a direction of the first height. In an embodiment, the apparatus includes a second bump field with a second height and a second depth on the substrate, where the second depth is orthogonal to the second height, and where the second bump field comprises a second pitch in a direction of the second height, where the second pitch is smaller than the first pitch. Embodiments include a third bump field with a third height and the second depth, where a sum of the second height and the third height is equal to the first height.

公开(公告)号：US20250142846A1

公开(公告)日：2025-05-01

申请号：US18383714

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Basavaraj KANTHI ,  Andrew P. COLLINS ,  Jian Yong XIE

IPC: H01L27/10

Abstract: Embodiments disclosed herein include a capacitor apparatus. In an embodiment, the apparatus comprises a first metal layer and a first plate above the first metal layer, where the first plate is electrically conductive. In an embodiment, a second plate is above the first plate, where the second plate is electrically conductive, and a third plate is above the second plate, where the third plate is electrically conductive. In an embodiment, a second metal layer is above the third plate, and a first via is between the first metal layer and the second metal layer, where the first via contacts the first plate and the third plate. In an embodiment, a second via is between the first metal layer and the second metal layer, where the second via contacts the second plate, and a third via is between the first metal layer and the first plate.