公开(公告)号：US20180314903A1

公开(公告)日：2018-11-01

申请号：US15582945

申请日：2017-05-01

Applicant: INTEL CORPORATION

Inventor： Gurpreet S. Kalsi ,  Om J. Omer ,  Biji George ,  Gopi Neela ,  Dipan Kumar Mandal ,  Sreenivas Subramoney

IPC: G06K9/00 ,  G06K9/46

CPC classification number: G06K9/00973 ,  G06K9/4604 ,  G06K9/4647

Abstract: One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.

公开(公告)号：US20200226203A1

公开(公告)日：2020-07-16

申请号：US16833210

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Biji George ,  Om Ji Omer ,  Dipan Kumar Mandal ,  Cormac Brick ,  Lance Hacking ,  Sreenivas Subramoney ,  Belliappa Kuttanna

IPC: G06F17/16

Abstract: A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

公开(公告)号：US10318834B2

公开(公告)日：2019-06-11

申请号：US15582945

申请日：2017-05-01

Applicant: INTEL CORPORATION

Inventor： Gurpreet S. Kalsi ,  Om J. Omer ,  Biji George ,  Gopi Neela ,  Dipan Kumar Mandal ,  Sreenivas Subramoney

IPC: G06K9/00 ,  G06K9/46 ,  G06F17/10

Abstract: One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.

公开(公告)号：US12140696B2

公开(公告)日：2024-11-12

申请号：US17375017

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Chulong Chen ,  Wenling Margaret Huang ,  Saiveena Kesaraju ,  Ivan Simões Gaspar ,  Pradyumna S. Singh ,  Biji George ,  Dipan Kumar Mandal ,  Om Ji Omer ,  Sreenivas Subramoney ,  Yuval Amizur ,  Leor Banin ,  Hao Chen ,  Nir Dvorecki ,  Shengbo Xu

IPC: G01S7/41 ,  G01S7/40 ,  G01S13/58 ,  G01S13/89 ,  H01Q15/02 ,  H01Q21/06

Abstract: According to various embodiments, a radar device is described comprising a processor configured to generate a scene comprising an object based on a plurality of receive wireless signals, generate a ground truth object parameter of the object and generate a dataset representative of the scene and a radar detector configured to determine an object parameter of the object using a machine learning algorithm and the dataset, determine an error value of the machine learning algorithm using a cost function, the object parameter, and the ground truth object parameter and adjust the machine learning algorithm values to reduce the error value.

公开(公告)号：US11347828B2

公开(公告)日：2022-05-31

申请号：US16833210

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Biji George ,  Om Ji Omer ,  Dipan Kumar Mandal ,  Cormac Brick ,  Lance Hacking ,  Sreenivas Subramoney ,  Belliappa Kuttanna

IPC: G06F17/16

Abstract: A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

公开(公告)号：US20220114234A1

公开(公告)日：2022-04-14

申请号：US17560100

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Biji George ,  Sreenivas Subramoney ,  Om Ji Omer ,  Anoop Viswam

IPC: G06F17/16 ,  G06F7/544

Abstract: A matrix processing engine is provided for efficient matrix computation performed by a dense matrix compute circuit (performing SIMD operations) and a scalar computing core (performing SISD operations). These two processing components operate together to produce output data tiles by feeding results of the dense SIMD operations to the scalar computing core using thread packing and an in-line buffer for accumulating and packing the dense result data. This permits the scalar computing to spawn threads to operate on the dense results as available and without requiring partial or intermediate data read/writes between the dense and scalar computations.