公开(公告)号：US20190258504A1

公开(公告)日：2019-08-22

申请号：US16398017

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Bishwajit Dutta

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/445

Abstract: Techniques and mechanisms for communicating compiled software instructions via a network, wherein the compiled instructions are to execute a kernel process of a network device. In an embodiment, a first node of a network receives a kernel source code from a second node of the network. The first node compiles the kernel source code to generate a kernel binary code, which is provided to the second node. Based on the kernel binary code being communicated to the second node, a software developer is able to perform a simulation that facilitates the development of an application binary code. The first node subsequently receives the application binary and an indication that the application binary is to be executed with the kernel binary at the first node. In some embodiments, the first node executes an application process and a kernel process to provide an application offload resource for another network node.

公开(公告)号：US20200319815A1

公开(公告)日：2020-10-08

申请号：US16903329

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bishwajit Dutta ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: An apparatus comprises a controller comprising an interface comprising circuitry to communicate with a host computing device; and a relocation manager comprising circuitry, the relocation manager to provide, for the host computing device, an identification of a plurality of data blocks to be relocated within a non-volatile memory; and relocate at least a subset of the plurality of data blocks in accordance with a directive provided by the host computing device in response to the identification of the plurality of data blocks to be relocated.

公开(公告)号：US11210130B2

公开(公告)日：2021-12-28

申请号：US16855139

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Bishwajit Dutta ,  Sanjeev N. Trika ,  Anand S. Ramalingam ,  Pallav H. Gala

IPC: G06F9/46 ,  G06F3/06 ,  G06F9/54 ,  G06F9/48

Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.

公开(公告)号：US11003479B2

公开(公告)日：2021-05-11

申请号：US16398017

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Bishwajit Dutta

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/445

Abstract: Techniques and mechanisms for communicating compiled software instructions via a network, wherein the compiled instructions are to execute a kernel process of a network device. In an embodiment, a first node of a network receives a kernel source code from a second node of the network. The first node compiles the kernel source code to generate a kernel binary code, which is provided to the second node. Based on the kernel binary code being communicated to the second node, a software developer is able to perform a simulation that facilitates the development of an application binary code. The first node subsequently receives the application binary and an indication that the application binary is to be executed with the kernel binary at the first node. In some embodiments, the first node executes an application process and a kernel process to provide an application offload resource for another network node.

公开(公告)号：US12118240B2

公开(公告)日：2024-10-15

申请号：US16987748

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Benjamin Walker ,  Sanjeev Trika ,  Kapil Karkra ,  James R. Harris ,  Steven C. Miller ,  Bishwajit Dutta

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0689

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.