公开(公告)号：US20240085972A1

公开(公告)日：2024-03-14

申请号：US17944310

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Yashwitha Suvarna ,  Boon Hui Ang ,  Pranali Shah

IPC: G06F1/3296 ,  G06F9/52

CPC classification number: G06F1/3296 ,  G06F9/52 ,  G06F2209/5018 ,  G06F2209/5021

Abstract: Embodiments described herein may include apparatus, systems, techniques or processes that are directed to chiplet state aware and dynamic prioritization of voltage regulator event indication handling. An intelligent arbiter notifies chiplets of VR events in a dynamic priority scheme that considers multiple factors such as chiplet state (for example, active, sleep, deep sleep, and the like), chiplet power consumption and time frame for transitioning to an active state, outstanding VR requests, chiplet latency sensitivity and the like in its prioritization of chiplet notifications. As chiplet states themselves are dynamic with a chiplet transitioning between multiple states during operation, the intelligent arbiter may also utilize a dynamic prioritization scheme to maximize efficiency and minimize power consumption.