公开(公告)号：US10009194B2

公开(公告)日：2018-06-26

申请号：US15332376

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Yun He ,  Sanjib Sarkar ,  Fei Deng ,  Senthil Arun Singaravelu ,  Narender Nagulapally ,  Pranali Shah

IPC: H04L25/03 ,  H04L7/00 ,  G06F13/40 ,  H04L7/033 ,  H04L7/027

CPC classification number: H04L25/03057 ,  G06F13/4072 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0332 ,  H04L25/03949

Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

公开(公告)号：US09479364B2

公开(公告)日：2016-10-25

申请号：US14711259

申请日：2015-05-13

Applicant: Intel Corporation

Inventor： Yun He ,  Sanjib Sarkar ,  Fei Deng ,  Senthil Arun Singaravelu ,  Narender Nagulapally ,  Pranali Shah

IPC: H04L25/03 ,  H04L7/00 ,  G06F13/40 ,  H04L7/033 ,  H04L7/027

CPC classification number: H04L25/03057 ,  G06F13/4072 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0332 ,  H04L25/03949

Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

公开(公告)号：US20240085972A1

公开(公告)日：2024-03-14

申请号：US17944310

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Yashwitha Suvarna ,  Boon Hui Ang ,  Pranali Shah

IPC: G06F1/3296 ,  G06F9/52

CPC classification number: G06F1/3296 ,  G06F9/52 ,  G06F2209/5018 ,  G06F2209/5021

Abstract: Embodiments described herein may include apparatus, systems, techniques or processes that are directed to chiplet state aware and dynamic prioritization of voltage regulator event indication handling. An intelligent arbiter notifies chiplets of VR events in a dynamic priority scheme that considers multiple factors such as chiplet state (for example, active, sleep, deep sleep, and the like), chiplet power consumption and time frame for transitioning to an active state, outstanding VR requests, chiplet latency sensitivity and the like in its prioritization of chiplet notifications. As chiplet states themselves are dynamic with a chiplet transitioning between multiple states during operation, the intelligent arbiter may also utilize a dynamic prioritization scheme to maximize efficiency and minimize power consumption.

公开(公告)号：US20170070370A1

公开(公告)日：2017-03-09

申请号：US15332376

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Yun He ,  Sanjib Sarkar ,  Fei Deng ,  Senthil Arun Singaravelu ,  Narender Nagulapally ,  Pranali Shah

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L25/03057 ,  G06F13/4072 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0332 ,  H04L25/03949

Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

Abstract translation: 串行输入/输出方法和接收器包括接收模拟差分串行输入并对输入进行采样以提供数据和误差信号的接收器部分，响应于数据和误差信号的均衡反馈回路以调整接收器部分，相位反馈 与均衡反馈环路分离以提供相位误差，以及时钟数据恢复块，其耦合以接收相位误差，以独立于均衡反馈来执行接收器部分的定时恢复以调整采样。