公开(公告)号：US20220336668A1

公开(公告)日：2022-10-20

申请号：US17850799

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Bruce E. BEATTIE ,  Leonard GULER ,  Biswajeet GUHA ,  Jun Sung KANG ,  William HSU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

公开(公告)号：US20240145598A1

公开(公告)日：2024-05-02

申请号：US18404619

申请日：2024-01-04

Applicant: Intel Corporation

Inventor： Bruce E. BEATTIE ,  Leonard GULER ,  Biswajeet GUHA ,  Jun Sung KANG ,  William HSU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.