公开(公告)号：US20190042087A1

公开(公告)日：2019-02-07

申请号：US15843545

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： ZHENYU ZHU ,  CHAI HUAT GAN ,  MIKAL HUNSAKER

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/42

Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.