公开(公告)号：US20190052277A1

公开(公告)日：2019-02-14

申请号：US16017865

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： JAGANNADHA RAO RAPETA ,  ASAD AZAM ,  AMIT KUMAR SRIVASTAVA ,  MIKAL HUNSAKER

IPC: H03L7/08 ,  G05B9/03 ,  H03L7/081

Abstract: Methods and apparatus relating to functional safety clocking framework for real time systems are described. In an embodiment, clock monitoring logic circuitry monitors a plurality of clock signals. Safety island logic circuitry receives an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals. Safety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190042087A1

公开(公告)日：2019-02-07

申请号：US15843545

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： ZHENYU ZHU ,  CHAI HUAT GAN ,  MIKAL HUNSAKER

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/42

Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.