公开(公告)号：US12216579B2

公开(公告)日：2025-02-04

申请号：US17134254

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Samantika S. Sury ,  Christopher J. Hughes ,  Lingxiang Xiang ,  Rahul Agrawal

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862

Abstract: Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

公开(公告)号：US20220206945A1

公开(公告)日：2022-06-30

申请号：US17134254

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Samantika S. Sury ,  Christopher J. Hughes ,  Lingxiang Xiang ,  Rahul Agrawal

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/084

Abstract: Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

公开(公告)号：US10705962B2

公开(公告)日：2020-07-07

申请号：US15850865

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Robert G. Blankenship ,  Chyi-Chang Miao ,  Chitra Natarajan ,  Anthony-Trung D. Nguyen

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/123 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/127

Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.

公开(公告)号：US20190196968A1

公开(公告)日：2019-06-27

申请号：US15850865

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Robert G. Blankenship ,  Chyi-Chang Miao ,  Chitra Natarajan ,  Anthony-Trung D. Nguyen

IPC: G06F12/084 ,  G06F12/123 ,  G06F12/128 ,  G06F12/0811

Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.