公开(公告)号：US20130297878A1

公开(公告)日：2013-11-07

申请号：US13934198

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US09069671B2

公开(公告)日：2015-06-30

申请号：US14337174

申请日：2014-07-21

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US08799577B2

公开(公告)日：2014-08-05

申请号：US13934198

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US10705962B2

公开(公告)日：2020-07-07

申请号：US15850865

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Robert G. Blankenship ,  Chyi-Chang Miao ,  Chitra Natarajan ,  Anthony-Trung D. Nguyen

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/123 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/127

Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.

公开(公告)号：US20190196968A1

公开(公告)日：2019-06-27

申请号：US15850865

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Robert G. Blankenship ,  Chyi-Chang Miao ,  Chitra Natarajan ,  Anthony-Trung D. Nguyen

IPC: G06F12/084 ,  G06F12/123 ,  G06F12/128 ,  G06F12/0811

Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.