公开(公告)号：US20240427636A1

公开(公告)日：2024-12-26

申请号：US18213189

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Fangfei LIU ,  Carlos ROZAS ,  Thomas UNTERLUGGAUER ,  Scott CONSTABLE

IPC: G06F9/50

Abstract: An apparatus and method for securely reserving resources for trusted execution. For example, one embodiment of a processor comprises: a plurality of cores, each core of the plurality of cores to provide at least one logical processor of a plurality of logical processors; a first plurality of registers, each register of the first plurality of registers to associate a class of service (CLOS) value with a corresponding logical processor of the plurality of logical processors; a second plurality of registers, each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding CLOS value; a first control register of a first logical processor of the plurality of logical processors to be configured with a reserved CLOS value associated with a trusted control structure; resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved CLOS value; and enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved CLOS value.

公开(公告)号：US20200004552A1

公开(公告)日：2020-01-02

申请号：US16024733

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Fangfei LIU ,  Bin XING ,  Michael STEINER ,  Mona VIJ ,  Carlos ROZAS ,  Francis MCKEEN ,  Meltem OZSOY ,  Matthew FERNANDEZ ,  Krystof ZMUDZINSKI ,  Mark SHANAHAN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.